21-06-2013, 12:51 PM
VLIW ARCHITECTURE
VLIW ARCHITECTURE.PPT (Size: 268 KB / Downloads: 12)
Increasing Processor Performance
Semiconductor Technology
Parallel Processing
Multiprocessors, Multicomputers
Parallelism within the Processor
Pipelining
ILP
Scalar Processors
Fetching and executing an instruction at a time
A program represents a plan of execution.
The processor acts as an interpreter that executes the instruction in the program one at a time.
Superscalar processors
Decision about operations by H/W
More than one instruction at a time
Dynamic scheduling
Disadvantages of Superscalar
Complexity of hardware.
Window size constrained. This limits the capacity to detect independent instructions.
More power consumption.
VLIW
Very Long Instruction Word.
Instructions hundereds of bits in length
Uses long instruction called a Multiop
Multiple functional units are concurrently used
Functional units share a common register file.
Code compaction by compiler.
A Brief History
Joseph fisher,Trace scheduling,1979
He coined the acronym VLIW.
In 1984, two companies were started
Multiflow, started by Joseph Fisher
Cydrome, founded by Bob Rau.
Shortcomings
Wasteful encoding with NOPs.
Hard to maintain code compatibility between generations.
Increased program size.
Compiler has to explicitly add NOP.
New versions of the architecture can force major rewriting of the compiler.
Future of VLIW
Newer processors are mainly used for
Stream and image processing. Eg PhilipsTrimedia
Digital Signal Processig. Eg TMS320C62x from Texas Instr
Mobile computing. Eg Transmeta Crusoe
High end server applications. Eg Intel Itanium