15-09-2014, 12:47 PM
VLSI Architecture for Spread Spectrum Image Watermarking in Walsh-Hadamard
Transform Domain using Binary Watermark Project Report
VLSI Architecture for Spread.pdf (Size: 326.76 KB / Downloads: 14)
Abstract
Spread-spectrum communication encompasses a
number of signalling techniques in which the transmitted
bandwidth is significantly larger than required by the data
rate and the transmitted bandwidth is determined by a
function independent of the message that is known to both
sender and receiver. Originally intended to increase resistance
to jamming and lowering the probability of interception, its
properties are also desirable in a number of other applications
and have been applied to the problem of digital watermarking.
In this paper we have a transform domain Spread Spectrum
(SS) watermarking scheme which effectively eliminates
security problem while increasing robustness and enhancing
perceptual quality of watermarked image. VLSI
implementation using Field Programmable Gate Array
(FPGA) has been developed for the proposed watermarking
algorithm which becomes a solution for real-time
implementation
PROPOSED VLSI ARCHITECTURE
The architecture of the proposed watermarking
algorithm is shown in figure.1 The main building blocks are
as follows: (A) Controller (B) Memory Block (i) Memory
Cover (ii) Memory Watermark (iii) Memory Compare ©
Assembly and Compare Block (D) Code block (E) Walsh
Hadamard Transform block. A detailed description of
individual elements is also presented.
Memory Block
The memory cover is 216 x 8 bits memory which stores
the cover image data of 8 bits. Next we have the memory
water which is 212 x 4 bit long. Here the watermark image is
binary image which is represented by 4 bits. Lastly we have
the Memory Compare which stores 4 bit comparison data
from the assembly and compare block. It is 210 x 4bit
memory
ANALYSIS AND RESULTS
We consider a 1 bit/pixel of size (64 x 64) and 8bits/pixel of
size (256 x 256) binary and greyscale images as watermark
and the cover image respectively for experiment purpose.
The partitioning of the cover i.e. (8x8) and the watermark
image followed by the conversion of the integer image data
to binary was done with the help of MATLAB. With the
binary image data for both the partitioned cover and the
partitioned watermark image, we put them in the test bench
as input cover and input watermark image.
The synthesis of the watermark embedding have been
implemented on Xilinx (ISE version14.1) based FPGA
platform. We have chosen Virtex4 series of FPGA to fit the
complexities of the design. The device used is XC4vlx200-
11ff1513for the implementation and the language used is
VHDL. The behavioral simulation was done with
SYNOPSYS VCS-MX to verify the functionality of the
design. A test bench is also written in VHDL to give the
input vectors for the simulated program. The FPGA
implementation of the architecture, for (8 x 8) block of the
cover image for binary watermark, consumes 1146 mW
power and results in a clock frequency of 90.131 MHz
CONCLUSION
The paper proposes a Walsh-Hadamard transform
domain image watermarking scheme by combined use of
channel coding and spread spectrum modulation. The
algorithm is simple with low computation cost and can be
easily implemented in hardware. VLSI design of the
proposed algorithm using FPGA is also developed and thus
makes it suitable for real time authentication as well as
secured communication.