27-05-2014, 12:55 PM
VLSI Design of Low Power Booth Multiplier
VLSI Design of Low Power .pdf (Size: 599.42 KB / Downloads: 69)
Abstract
This paper proposes the design and implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix
2 and modified radix 4 Booth multipliers. Experimental results demonstrate that the modified radix 4 Booth multiplier has 22.9% power reduction than the
conventional radix 2 Booth Multiplier.
INTRODUCTION
Continuous advances of microelectronic technologies make
better use of energy, encode data more effectively, transmit
information more reliable, etc. Particularly, many of these
technologies address low-power consumption to meet the
requirements of various portable applications [5]. In these
application systems, a multiplier is a fundamental
arithmetic unit and widely used in circuits.
VHDL is one of the common techniques for the
digital system emergent process. The technique is done by
program using certain software which performs simulation
and examination of the designed system. The designer only
needs to describe his digital circuit design in textual form
which can remove without the effort to alter the hardware.
VHDL is more preferred because this technique can reduce
cost and time, easy to troubleshoot, portable, a lot of
platform software support the VHDL function and high
references availability. All the processes will be running
using Xilinx ISE 8.2i software which means the process is
simulated only without any hardware implementation.
CONCLUSION
In this paper, the conventional and modified b ooth
multipliers are designed using VHDL. The delay and
power dissipation of modified radix 4 Booth multiplier is
less as compared to the conventional one. When
implemented on FPGA, it is found that the radix 4 booth
multiplier consumes 22.9% less power than conventional
radix 2 multiplier. Also estimated delay is less for radix 4
multiplier.