10-05-2013, 12:49 PM
VLSI IMPLEMENTATION OF LOW POWER MULTIPLIER
VLSI IMPLEMENTATION.pdf (Size: 375.51 KB / Downloads: 55)
ABSTRACT
Multiplier is one of the key logic blocks in most digital and high performance systems.
Among them booth multiplier is widely used. Here, radix 2 booth multiplier based on
conventional carry select adder and also based on modified carry select adder has been
developed. The carry select adder is used in partial product addition of booth multiplier.
The designs are tested and compared using NClaunch in cadence. Results show that
modified carry select adder based on binary to excess 1 converter is efficient than
conventional adder.
INTRODUCTION
Multipliers offer either of the following- high speed, low power consumption, less area
or even combination of them. This makes them suitable for various high speed, low power,
and compact VLSI implementations. Area and speed are the two main constraints of any
multiplier and optimizing them is a major design issue. Here, the booth multiplier is optimized
by using Carry Select Adder.
Carry Select Adder is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. It alleviates the problem of carry propagation
delay by independently generating multiple carries and then selects a carry to generate the
sum [1]. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. Carry-select method has deemed to be a good
compromise between cost and performance in carry propagation adder design. The square
root CSLA requires less power, area and has balanced delay [2], [3]. However, conventional
carry-select adder is still area consuming due to the dual Ripple Carry Adder (RCA)
structure. In order to reduce the area and power consumption the dual array of RCA is
replaced by a single array of RCA and an array of Binary to Excess 1 Converter (BEC) [4]-
[6].
CONVENTIONAL CARRY SELECT ADDER
In conventional Carry select adder, blocks of bits are added in two ways: one
assuming a carry-in of 0 and the other with a carry-in of 1.This results in two pre-computed
sum and carry-out signal pairs. The correct output is selected based on the original carry-in.
Generally multiplexers are used to propagate carries.
Fig.2 shows the internal logic schematic of a carry select adder constructed using the
conventional ripple carry adder (RCA). The RCA uses multiple full adders to perform
addition operation. Each full adder inputs a carry-in, which is the carry-out of the preceding
adder. The CSA divides the words to be added into blocks and forms two sums for each
block in parallel, one with assumed carry in (Cin) of 0 and the other with Cin of 1. As shown
in Fig. 2, the carry-out from one stage of RCA is used as the select signal for the multiplexer.
This selects the corresponding sum bit from the next block of data. This speeds-up the
computation process of the adder. Thus, the carry select adder achieves higher speed of
operation at the cost of increased number of devices used in the circuit. This in turn increases
the area and power consumed by the circuits of this type of structure.
IMPLEMENTATION RESULTS
The radix 2 booth multiplier using carry select adder and modified carry select adder
has been designed in Verilog HDL and synthesized in Cadence using NClaunch. The results
of the simulation and synthesis are given in Fig.5 and Table 2 respectively.Results show that
the booth multiplier using modified CSLA occupies less area and consumes less power
compared to regular CSLA. The power consumed is a sum of leakage and dynamic power.
This proves that carry select adder using binary to excess 1 converter is efficient for VLSI
implementation.