21-12-2012, 02:37 PM
VLSI Implementation of Adders for High Speed ALU
VLSI Implementation of Adders for High Speed ALU.pdf (Size: 294.63 KB / Downloads: 73)
ABSTRACT
This paper is primarily deals the construction of high speed
adder circuit using Hardware Description Language (HDL)
in the platform Xilinx ISE 9.2i and implement them on
Field Programmable Gate Arrays (FPGAs) to analyze the
design parameters. The motivation behind this investigation
is that an adder is a very basic building block of Arithmetic
Logic Unit (ALU) and would be a limiting factor in
performance of Central Processing Unit (CPU).
Design of a high speed single core processor is the future
goal of this paper. Single core processor would have many
advantages over a multiple-core approach. Task execution
on a single core is a well understood process, while
execution on many cores is a problem that has not yet been
solved. There are also computational tasks which
parallelize very badly, where a single high clock rate
processor would suit them very well. Such a high speed
processor needs certain components that should support
high speed. The two main components of processors are the
ALU and the register file. The one of the critical path
within an ALU may be the carry-chain in addition
operation.
INTRODUCTION
Digital computer ALU is an aspect of logic design with the
objective of developing appropriate algorithms in order to
achieve an efficient utilization of the available hardware.
The hardware can only perform a relatively simple and
primitive set of Boolean operations and the arithmetic
operations are based on a hierarchy of operations that are
built by using algorithms against the hardware. Since,
ultimately, speed, power and utilization of ALU are the
most often used measures of the efficiency of an algorithm.
COMPLEX ADDERS
The reference to eve of adding single bits, let‟s extend it to
adding binary words. In general, adding two n-bit words
yields an n-bit sum and a carry-out bit Cn. The carry is
carried from lower bit adder to higher bit adder. Based on
carry transfer from LSB to MSB, the adders are classified.
Ripple Carry Adder
It is possible to create a logical circuit using multiple full
adders to add N-bit numbers. Each full adder inputs a carry
Cin which is the Cout of the previous adder. This kind of
adder is a Ripple Carry Adder (RCA) in [9], since each
carry bit "ripples" to the next full adder. Note that the first
(and only the first) full adder may be replaced by a half
adder. The layout of a ripple carry adder is simple, which
allows fast design time. However, the ripple carry adder is
relatively slow, since each full adder must wait for the
carry bit which is coming from the previous full adder.
Carry – Select Adder
Carry Select Adders (CSA) use multiple narrow
adders to create fast wide adders. Consider the addition of
two n bit numbers with a = an-1…..a0, and b = bn-1…..b0. At
the bit level the adder delay increases from the least
significant 0th position upward, with the (n-1)th requiring
the most complex logic. A carry select adder breaks the
addition problem into smaller groups. A carry-select adder
provides two separate adders for the upper words, one for
each possibility. A multiplexer (MUX) is then used to
select the valid result. The figure 6 shows the block
diagram of CSA.
As a concrete example, consider an 8-bit adder
that is split into two 4-bit groups. The lower order bits a3 a2
a1 a0 and b3 b2 b1 b0 are fed into the 4-bit adder to produce
the sum bits S3 S2 S1S0 and a carry-out bit C4 as shown.