20-08-2013, 04:51 PM
VLSI Realization of a Secure Cryptosystem for Image Encryption and Decryption
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INTRODUCTION
The use of chaotic signal for secure data transmission has
seen a significant growth in developing chaos-based encryption
and decryption algorithms. However, a number of chaos-based
algorithms have been shown to be insecure [1-5]. A modified
chaotic key based algorithm with increased key size is
developed in [6] for improved security and VL SI architecture
of it is developed and realized using Xilinx I SE VL SI software
A cryptosystem based on Brahmagupta-Bhaskara (BB)
equation is proposed in [7]. The cryptosystem proposed in [7]
was subsequently improved in [8] to avoid known plaintext
attacks reported in [9]. However, It is shown in [10] that the
two cryptosystems proposed in [7] and [8] are vulnerable to
known plaintext attacks. Equation-based approaches, with
moderate size of keys; it is possible to develop algorithms with
high security.
VL SI ARCHI TECTURE O F THE PROPOSED
ENCRYPTION AND DECRYPTION ALGORITHMS
The proposed VL SI architectures have two key modules,
one for the generation of chaotic bits (CB), and the other for
encryption or decryption. The architecture of the chaotic bits
(CB) generator is the same as given in [1] where in the word
lengths of x(O) and f1 are 32. The concept of parallel
processing is adopted so that the encryption or decryption of 16
data values can be performed at the same time. Fig. 1 shows
the hardware architecture of the encryption unit (EU). This
architecture consists of one 32 bit parallel-in parallel-out
register, and 16 encryption processing elements (EPEs). The
hardware architecture of decryption unit (OU) is similar to the
structure shown in Fig. I except that the EPEs are replaced by
decryption processing elements (OPEs) with the encrypted data
as the input.
CONCLUSION S
In this paper a secure cryptosystem based on BB equation
and chaos with moderate size of keys is reported and for real
time use of the system, VL SI architecture of the cryptosystem
is designed and realized using Xilinx I SE VL SI software on an
image. The hardware complexity of the system is compared
with another cryptosystem. The complexity of the reported
algorithm is high with high security.