12-12-2012, 06:37 PM
VLSI System Design
VLSI System Design.pdf (Size: 118.29 KB / Downloads: 28)
Introduction
Chip designers face a bewildering array of choices
– What is the best circuit topology for a function?
– How many stages of logic give least delay?
How wide should the transistors be?
? ? ?
– • Logical effort is a method to make these
decisions
– Uses a simple model of delay
– Allows back-of-the-envelope calculations
– Helps make rapid comparisons between
alternatives
Computing Logical Effort
DEF: Logical effort is the ratio of the input capacitance of a
gate to the input capacitance of an inverter delivering the
same output current.
• Measure from delay vs. fanout plots
• Or estimate by counting transistor widths