06-02-2013, 12:54 PM
VLSI Testing and Design for Testability
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Fault
•Fault: a physical defectin a circuit/system
−Permanent fault: a fault that is continuous and stable, whose nature do not change before, during, and after testing
∗Affecting the functional behavior of the system permanently
∗A.k.a. hard faultor solid fault
∗Usually quite localized
∗Can be modeled
−Temporary fault: a fault that is present only part of the time, occurring at random moments and affecting the system for finite, but unknown, intervals of time
∗Transient fault: caused by environmental conditions
∗No well-defined fault model
∗Called soft errorin RAM
∗Often assumed no permanent damage was done
−Intermittent fault:caused by non-environmental conditions
∗Often repeatable
∗Can use permanent fault models and repeated test with stress
Fault Model and Error
•Fault model: logical effect of a fault
−Structure faults
∗Stuck-at faults: stuck-at-0 and stuck-at-1
∗Bridging (short) fault
∗Open (break) fault
∗Transistor stuck-on and stuck-open faults
∗Transition and delay faults
−Functional faults
∗RAM coupling and pattern-sensitive faults
∗PLA cross-point faults
•Error: manifestation of a fault that results in an incorrect module output or system state
Defect Level and Fault Coverage
•Defect level(DL) is the fraction of bad parts among the parts that pass all tests and are shipped
−DL= 1 –Y*(1-FC)
•FC refers to the real defect coverage (probability that Tdetects any possible fault---in For not)
•DL is measured in terms of DPM (defects per million), and typical values claimed are less than 200 DPM, or 0.02%
The Testing Problem
•Given a set of faults in the circuit under test (CUT), how do we obtain a certain (small) number of test patterns which guarantees a certain (high) fault coverage?
−What faults to test? (fault modeling)
−How are test patterns obtained? (test pattern generation)
−How is test quality (fault coverage) measured? (fault simulation)
−How are test vectors applied and results evaluated? (ATE/BIST)