25-01-2013, 02:27 PM
Verilog 1 - Fundamentals
1Verilog.pdf (Size: 1.68 MB / Downloads: 416)
The current situation
Simulators and other tools are available at all levels but not compilers from the behavioral level to RTL
Verilog Fundamentals
History of hardware design languages
Data types
Structural Verilog
Simple behaviors
Our Verilog Subset
Verilog is a big language with many
features not concerned with
synthesizing hardware.
The code you write for your processor
should only contain the languages
structures discussed in these slides.
Anything else is not synthesizable,
although it will simulate fine.
Verilog Registers “reg”
Wires are line names – they do not
represent storage and can be assigned
only once
Regs are imperative variables (as in C):
“nonblocking” assignment r <= v
can be assigned multiple times and holds
values between assignments