28-04-2014, 12:15 PM
Verilog HDL Dataflow Modeling
Why Dataflow ?
Rationale of dataflow: any digital system can be constructed
by interconnecting registers and a combinational logic put
between them for performing the necessary functions.
Dataflow provides a powerful way to implement a design.
Logic synthesis tools can be used to create a gate-level
circuit from a dataflow design description.
RTL (register transfer level) is a combination of dataflow
and behavioral modeling.
Continuous Assignments
An implicit continuous assignment
is the shortcut of declaring a net first and then writing a
continuous assignment on the net.
is always active.
can only have one implicit declaration assignment per net.
Vectors
A vector (multiple bit width) describes a bundle of signals as
a basic unit.
[high:low] or [low:high]
The leftmost bit is the MSB.
Both nets and reg data types can be declared as vectors.
The default is 1-bit vector or called scalar.
Arithmetic Operators
Arithmetic operators
If any operand bit has a value x, then the result is x.
The operators + and – can also used as unary operators to
represent signed numbers.
Modulus operators produce the remainder from the
division of two numbers.
In Verilog HDL, 2’s complement is used to represent
negative numbers.