10-01-2014, 12:25 PM
Verilog Tutorial
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Introduction
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description Language
is a language used to describe a digital system, for example, a network switch, a microprocessor
or a memory or a simple flip−flop. This just means that, by using a HDL one can describe any
hardware (digital ) at any level.
Gate Level
Within the logic level the characteristics of a system are described by logical links and their timing
properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X',
`Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates). Using gate
level modeling might not be a good idea for any level of logic design. Gate level code is generated
by tools like synthesis tools and this netlist is used for gate level simulation and for backend.
History Of Verilog
Verilog was started initially as a proprietary hardware modeling language by Gateway Design
Automation Inc. around 1984. It is rumored that the original language was designed by taking
features from the most popular HDL language of the time, called HiLo as well as from traditional
computer language such as C. At that time, Verilog was not standardized and the language
modified itself in almost all the revisions that came out within 1984 to 1990.
Verilog simulator was first used beginning in 1985 and was extended substantially through
1987.The implementation was the Verilog simulator sold by Gateway. The first major extension
was Verilog−XL, which added a few features and implemented the infamous "XL algorithm" which
was a very efficient method for doing gate−level simulation.
The time was late 1990. Cadence Design System, whose primary product at that time included
Thin film process simulator, decided to acquire Gateway Automation System. Along with other
Gateway product, Cadence now became the owner of the Verilog language, and continued to
market Verilog as both a language and a simulator. At the same time, Synopsys was marketing the
top−down design methodology, using Verilog. This was a powerful combination.
In 1990, Cadence recognized that if Verilog remained a closed language, the pressures of
standardization would eventually cause the industry to shift to VHDL. Consequently, Cadence
organized Open Verilog International (OVI), and in 1991 gave it the documentation for the Verilog
Hardware Description Language. This was the event which "opened" the language.
Simulation
Simulation is the process of verifying the functional characteristics of models at any level of
abstraction. We use simulators to simulate the the Hardware models. To test if the RTL code
meets the functional requirements of the specification, see if all the RTL blocks are functionally
correct. To achieve this we need to write testbench, which generates clk, reset and required test
vectors. A sample testbench for a counter is as shown below. Normally we spend 60−70% of time
in verification of design.