22-11-2012, 05:58 PM
Virtual Memory and Address Translation
Virtual Memory.pdf (Size: 329.98 KB / Downloads: 249)
Role of MMU Hardware and OS
VM address translation must be very cheap (on average).
• Every instruction includes one or two memory references.
(including the reference to the instruction itself)
VM translation is supported in hardware by a Memory
Management Unit or MMU.
• The addressing model is defined by the CPU architecture.
• The MMU itself is an integral part of the CPU.
The role of the OS is to install the virtual-physical mapping
and intervene if the MMU reports that it cannot complete
the translation.
The OS Directs the MMU
The OS controls the operation of the MMU to select:
(1) the subset of possible virtual addresses that are valid for
each process (the process virtual address space);
(2) the physical translations for those virtual addresses;
(3) the modes of permissible access to those virtual addresses;
read/write/execute
(4) the specific set of translations in effect at any instant.
need rapid context switch from one address space to another
MMU completes a reference only if the OS “says it’s OK”.
MMU raises an exception if the reference is “not OK”.
The Translation Lookaside Buffer (TLB)
An on-chip hardware translation buffer (TB or TLB) caches
recently used virtual-physical translations (ptes).
Alpha 21164: 48-entry fully associative TLB.
A CPU pipeline stage probes the TLB to complete over 99%
of address translations in a single cycle.
Like other memory system caches, replacement of TLB
entries is simple and controlled by hardware.
e.g., Not Last Used
If a translation misses in the TLB, the entry must be fetched
by accessing the page table(s) in memory.
cost: 10-500 cycles
What You Should Know
• Basics of paged memory management
• Typical address space layout
• Basics of address translation
• Architectural mechanisms to support paged memory
• Importance for kernel protection and process isolation
• Why the simple page table is inadequate
• Motivation for and structure of hierarchical tables
• Motivation for and structure of hashed (inverted) tables
Background
The remaining slides provide background from CPS 110.
Be sure you understand why page-based memory allocation is more
memory-efficient than the old way: allocating contiguous physical
memory for each address space (partitioning).
• Two partitioning strategies: fixed and variable
• How to make partitioning transparent to programs
• How to protect memory in a partitioned system
• Fragmentation: internal and external
• Fragmentation issues for each strategy
• Relevance to heap managers today
• Approaches to variable partitioning
Demand Paging and Page Faults
OS may leave some virtual-physical translations unspecified.
mark the pte for a virtual page as invalid
If an unmapped page is referenced, the machine passes control
to the kernel exception handler (page fault).
passes faulting virtual address and attempted access mode
Handler initializes a page frame, updates pte, and restarts.
If a disk access is required, the OS may switch to another process
after initiating the I/O.
Page faults are delivered at IPL 0, just like a system call trap.
Fault handler executes in context of faulted process, blocks on a
semaphore or condition variable awaiting I/O completion
Issues for Paged Memory Management
The OS tries to minimize page fault costs incurred by all
processes, balancing fairness, system throughput, etc.
(1) fetch policy: When are pages brought into memory?
prepaging: reduce page faults by bring pages in before needed
clustering: reduce seeks on backing storage
(2) replacement policy: How and when does the system select
victim pages to be evicted/discarded from memory?
(3) backing storage policy:
Where does the system store evicted pages?
When is the backing storage allocated?
When does the system write modified pages to backing store?