22-06-2012, 05:57 PM
Seminar on Design of Control Unit
Design of Control Unit.doc (Size: 117.5 KB / Downloads: 303)
To execute an instruction , the control unit of the CPU must generate the required control signal in the proper sequence. As for example , during the fetch phase , CPU has to generate PCout signal along with other required signal in the first clock pulse. In the second clock pulse CPU has to generate PCin signal along with other required signals. So, during fetch phase , the proper sequence for generating the signal to retrieve from and store to PC is PCout and PCin.
Hardwired Control :
In this hardwired control techniques , the control signals are generated by means of hardwired circuit. The main objective of control unit is to generate the control signal in proper sequence.
Consider the sequence of control signal required to execute the add instruction that is explained in previous lecture. It is obvious that eight non-overlapping time slots are required for proper execution of the instruction represented by this sequence.
Each time slot must be at least long enough for the function specified in the corresponding step to be completed. Since , the control unit is implemented by hardwire device and every device is having a propagation delay , due to which it requires some time to get the stable output signal at the output port after giving the input signal. So , to find out the time slot is a complicated design task.