08-08-2012, 03:26 PM
A HIGH SPEED LOW POWER MULTIPLIER-AND-ACCUMULATOR USING IMPROVISED RADIX-4 MODIFIED BOOTH ALGORITHM
A HIGH SPEED LOW POWER MULTIPLIER-AND-ACCUMULATOR .doc (Size: 348 KB / Downloads: 60)
INTRODUCTION
Multiplication is essential in many signal processing algorithms. These occupy large area, have more latency and consume more power. As a result low power multiplier is essential for designing low power VLSI system designs. A system performance mainly depends upon the performance of the multiplier since the multiplier is the slowest part of the design, optimizing the speed and area of the design consisting of multiplier is a major issue. Finally parallel multipliers were designed which improved by speed by increasing the area. However digit serial multiplier came into existence which has moderate performance in speed and area. Multiplier mainly classified into three stages PPG (Partial product generation), RPP (Reduction of partial products) and final accumulation of partial products. The amount of power consumed by the design depends upon the power consumed by the multiplier and the power consumed by the multiplier depends upon the number of partial products generated by that multiplier, as if the partial products generated by the multiplier are more, then much circuitry is needed to reduce the partial products, as a result of this the design occupies large area.
OVERVIEW OF MAC
In the above figure (1) x and y represents the multiplicand and multiplier which are given as inputs to the multiplier. The multiplier must be chosen such that it generates less partial products. Out of the available multipliers we preferred modified booth algorithm which produces partial products half (n/2) compared to array multiplier which generates n partial products for n bit multiplication[3]. The basic arithmetic steps involved in the MAC are shown in figure (2).In the first step multiplier is divided into segment of size 3 bits by appending bit ‘0’at the LSB. Based on the bits of the segment particular operation need to be performed on the multiplicand.
PROPOSED ARCHITECTURE
As we noticed that implementing the Wallace adder in the reduction of partial products played a vital role in the increase in performance of the design, there is a possibility that all the bits of the multiplicand and multiplier are not needed to be multiplied (i.e.) there are cases such as both the inputs are zeros or either of the input may be zero. In such cases as the result is constant there is an unnecessary usage of logic circuitry to generate the constant result, there may be the cases of either of the input may be one in that case we can avoid the computation and simply forward the other bit to the next level in which we can save power and the speed of the design was improved. In our proposed technique the accumulation was merged in the process of adding partial products . Figure(5) depicts the arithmetic steps of the proposed MAC
CONCLUSION
From this design we here by conclude that by implementing the controller in the multiplier and as well as the carry look ahead adder we can improve speed up to 20% and can reduce power up to 30%. By using the merged adder we can improve the performance of a system.