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Zigbee Wireless Vehicular Identification and Authentication System
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INTRODUCTION
Zigbee is a recently developed wireless technology used in many commercial and research applications. Based on the IEEE 802.15.4 specification it has become a very attractive wireless connectivity solution due to its open standard, low cost and low power characteristics. Zigbee is suitable for low data-rate and low power consumption applications in comparison with other wireless technologies such as Bluetooth and Wi-Fi. Applications include home and building automation, industrial control, building management systems, environmental monitoring, vehicle fleet management systems etc. Intelligent vehicle and fleet management systems are required by large companies, establishments and high security zones with restricted access, to identify, authenticate and manage their vehicle fleet and to control access to outsiders. With the advent of cheap low power commercial RF modules such fully automated management systems are being implemented using wireless technologies. Presents a novel bus priority control system for the Advanced Public Transportation System (APTS) based on wireless sensor networks and Zigbee, authors of report the use of Zigbee RF nodes for data packet transmission in an intra-car wireless en00vironment, investigates the suitability to Zigbee wireless technology for Intelligent Transportation Systems (ITS). We have proposed a system using Zigbee wireless RF tags to identify and authenticate vehicles entering into such a premises. Design consists of RF vehicle tags containing authentication information for each vehicle authorized, an RF tag reader, an RF tag writer and a central database containing information about all vehicles authorized to enter the facility. Prototype of the system was demonstrated under real conditions and results conclude that the proposed system is viable. The rest of the paper will be organized as follows, section II will give details of the system model.
CHAPTER 2
EMBEDDED SYSTEMS
An embedded system is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few predefined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass-produced, benefiting from economies of scale.
Personal digital assistants (pdas) or handheld computers are generally considered embedded devices because of the nature of their hardware design, even though they are more expandable in software terms. This line of definition continues to blur as devices expand. With the introduction of the OQO Model 2 with the Windows XP operating system and ports such as a USB port — both features usually belong to "general purpose computers", — the line of nomenclature blurs even more.
Physically, embedded systems ranges from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants . In terms of complexity embedded systems can range from very simple with a single microcontroller chip, to very complex with multiple units, peripherals and networks mounted inside a large chassis or enclosure.
Examples of Embedded Systems:
• Avionics, such as inertial guidance systems, flight control hardware/software and other integrated systems in aircraft and missiles
• Cellular telephones and telephone switches
• Engine controllers and antilock brake controllers for automobiles
• Home automation products, such as thermostats, air conditioners, sprinklers, and security monitoring systems
• Handheld calculators
• Handheld computers
• Household appliances, including microwave ovens, washing machines, television sets, DVD players and recorders
• Medical equipment
• Personal digital assistant
• Videogame consoles
• Computer peripherals such as routers and printers.
• Industrial controllers for remote machine operation.
CHAPTER 3
BLOCK DIAGRAM
3.1. RECEIVER SECTION:
3.2. TRANSMITTER SECTION:
Fig 3.2: block diagram of transmitter section
CHAPTER 4
BLOCK DIAGRAM DESCRIPTION
The Block diagram consists of a Zigbee tranceiver, Keypad, a Micro controller, an LCD Display and power supply. These hardware components will be discussed briefly as follows:
4.1. Microcontroller Section:
This section forms the control unit of the whole project. This section basically consists of a Microcontroller with its associated circuitry like Crystal with capacitors, Reset circuitry, Pull up resistors (if needed) and so on. The Microcontroller forms the heart of the project because it controls the devices being interfaced and communicates with the devices according to the program being written.
4.2. Power supply:
In this project we required operating voltage for ARM controller board is 12V. Hence the 12V D.C. power supply is needed for the ARM board . This regulated 12V is generated by stepping down the voltage from 230V to 18V now the step downed a.c voltage is being rectified by the Bridge Rectifier using 1N4007 diodes. The rectified a.c voltage is now filtered using a ‘C’ filter. Now the rectified, filtered D.C. voltage is fed to the Voltage Regulator. This voltage regulator provides/allows us to have a Regulated constant Voltage which is of +12V. The rectified; filtered and regulated voltage is again filtered for ripples using an electrolytic capacitor 100μf. Now the output from this section is fed to microcontroller board to supply operating voltage.
4.3. LCD Display Section:
This section is basically meant to show up the status of the project. This project makes use of Liquid Crystal Display to display / prompt for necessary information.
4.4. Zigbee transceiver:
Transceiver is a device which acts as both transmitter and receiver. This operates with 2.8-3.4V. Range of the transceiver module is 30-70m in urban areas and 1-1.5km in outdoor (LOS). The transceiver has an on-chip wire antenna and it operates at a frequency of 2.4ghz.The data received from the microcontroller is organized based on the ZIGBEE protocol standards and then modulated. Along with the data, source address and destination address are added and sent.
4.5. RFID Reader (Radio Frequency Identification):
Radio Frequency Identification (RFID) is a generic term for non-contacting technologies that use radio waves to automatically identify people or objects. The combined antenna and microchip are called an "RFID transponder" or "RFID tag" and work in combination with an "RFID reader".
Radio Frequency Identification (RFID) is the latest technology that is being adopted to track and trace materials, including books.
4.6. H-Bridge:
Each H-Bridge having two inputs. Micro controller gives input to H-Bridge to control the direction of the robot. Based on the given inputs to the H-Bridge, the motor will be rotates either in clock-wise or in anti-clock wise direction. So that the movement of the robot will be controlled.
4.7. Keypad:
In electronics, a switch is an electrical component that can break an electrical circuit, interrupting the current or diverting it from one conductor to another. The most familiar form of switch is a manually operated electromechanical device with one or more sets of electrical contacts. Each set of contacts can be in one of two states: either 'closed' meaning the contacts are touching and electricity can flow between them, or 'open', meaning the contacts are separated and non-conducting.
5.1.1. Schematic explanation:
In this project we required operating voltage for ARM controller board is 12V. Hence the 12V D.C. power supply is needed for the ARM board. This regulated 12V is generated by stepping down the voltage from 230V to 18V now the step downed a.c voltage is being rectified by the Bridge Rectifier using 1N4007 diodes. The rectified a.c voltage is now filtered using a ‘C’ filter. Now the rectified, filtered D.C. voltage is fed to the Voltage Regulator. This voltage regulator provides/allows us to have a Regulated constant Voltage which is of +12V. The rectified; filtered and regulated voltage is again filtered for ripples using an electrolytic capacitor 100μf. Now the output from this section is fed to microcontroller board to supply operating voltage.
• ZIGBEE is connected to the UART 0.
• RFID READER is connected to the UART 1.
• China motor is connected to the port P0.16 &P017.
5.2. RECEIVER SECTION:
5.2.1. Schematic explanation:
In this project we required operating voltage for ARM controller board is 12V. Hence the 12V D.C. power supply is needed for the ARM board . This regulated 12V is generated by stepping down the voltage from 230V to 18V now the step downed a.c voltage is being rectified by the Bridge Rectifier using 1N4007 diodes. The rectified a.c voltage is now filtered using a ‘C’ filter. Now the rectified, filtered D.C. voltage is fed to the Voltage Regulator. This voltage regulator provides/allows us to have a Regulated constant Voltage which is of +12V. The rectified; filtered and regulated voltage is again filtered for ripples using an electrolytic capacitor 100μf. Now the output from this section is fed to microcontroller board to supply operating voltage.
• ZIGBEE is connected to the UART 0.
• Keys are connected to the port P0.16 to P0.18.
CHAPTER 6
HARDWARE COMPONENTS
6.1. Arm processor overview:
ARM stands for Advanced RISC Machines. It is a 32 bit processor core, used for high end application.
It is widely used in Advanced Robotic Applications.
6.1.1. History and Development:
• ARM was developed at Acron Computers ltd of Cambridge, England between 1983 and 1985.
• RISC concept was introduced in 1980 at Stanford and Berkley.
• ARM ltd was found in 1990.
• ARM cores are licensed to partners so as to develop and fabricate new microcontrollers around same processor cores.
6.1.2. Key features:
1. 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
2. 8 kb to 40 kb of on-chip static RAM and 32 kb to 512 kb of on-chip flash memory.
128-bit wide interface/accelerator enables high-speed 60 mhz operation.
3. In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader
Software. Single flash sector or full chip erase in 400 ms and programming of
256 bytes in 1 ms.
4. Embeddedice RT and Embedded Trace interfaces offer real-time debugging with the
On-chip realmonitor software and high-speed tracing of instruction execution.
5. USB 2.0 Full-speed compliant device controller with 2 kb of endpoint RAM.
In addition, the LPC2146/48 provides 8 kb of on-chip RAM accessible to USB by DMA.
6. One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit adcs provide a total of 6/14
Analog inputs, with conversion times as low as 2.44 μs per channel.
7. Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
8. Two 32-bit timers/external event counters (with four capture and four compare
Channels each), PWM unit (six outputs) and watchdog.
9. Low power Real-Time Clock (RTC) with independent power and 32 khz clock input.
10. Multiple serial interfaces including two uarts (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities.
11. Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
12. Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
13. Up to 21 external interrupt pins available.
14. 60 mhz maximum CPU clock available from programmable on-chip PLL with settling Time of 100 μs.
15. On-chip integrated oscillator operates with an external crystal from 1 mhz to 25 mhz.
16. Power saving modes include Idle and Power-down.
17. Individual enable/disable of peripheral functions as well as peripheral clock scaling for Additional power optimization.
18. Processor wake-up from Power-down mode via external interrupt or BOD.
19. Single power supply chip with POR and BOD circuits:
20. CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O Pads.
6.2.2. Core Data path:
• Architecture is characterized by Data path and control path.
• Data path is organized in such a way that, operands are not fetched directly from memory locations. Data items are placed in register files. No data processing takes place in memory locations.
• Instructions typically use 3 registers. 2 source registers and 1 destination register.
• Barrel Shifter preprocesses data, before it enters ALU.
- Barrel Shifter is basically a combinational logic circuit, which can shift data to left or right by arbitrary number of position in same cycle.
• Increment or Decrement logic can update register content for sequential access.
6.2.3. Pipeline:
• In ARM 7, a 3 stage pipeline is used. A 3 stage pipeline is the simplest form of pipeline that does not suffer from the problems such as read before write.
• In a pipeline, when one instruction is executed, second instruction is decoded and third instruction will be fetched.
• This is executed in a single cycle.
6.2.4. Register Bank:
• ARM 7 uses load and store Architecture.
• Data has to be moved from memory location to a central set of registers.
• Data processing is done and is stored back into memory.
• Register bank contains, general purpose registers to hold either data or address.
• It is a bank of 16 user registers R0-R15 and 2 status registers.
• Each of these registers is 32 bit wide.
6.2.5. Data Registers- R0-R15:
• R0-R12 - General Purpose Registers
• R13-R15 - Special function registers of which,
R13 - Stack Pointer, refers to entry pointer of Stack.
R14 - Link Register, Return address is put to this when ever a subroutine is called.
R15 - Program Counter
Depending upon application R13 and R14 can also be used as GPR. But not commonly used.
In addition there are 2 status registers
• CPSR - Current program status register, status of current execution is stored.
• SPSR - Saved program Status register, includes status of program as well as processor.
6.2.6. CPSR:
CPSR contains a number of flags which report and control the operation of ARM7 CPU.
6.2.7. Conditional Code Flags:
N - Negative Result from ALU
Z - Zero result from ALU
C - ALU operation carried out
V - ALU operation overflowed
6.2.8. Interrupt Enable Bits:
I - IRQ, Interrupt Disable
F - FIQ, Disable Fast Interrupt
6.2.9. T- Bit:
If
T=0, Processor in ARM Mode.
T=1, Processor in THUMB Mode
6.2.10. Mode Bits:
Specifies the processor Modes. Processor Modes will be discussed in the next part of this tutorial.
6.3. VECTORED INTERRUPT CONTROLLER:
6.3.1 FEATURES:
1. ARM Prime Cell™ Vectored Interrupt Controller
2. 32 interrupt request inputs
3. 16 vectored IRQ interrupts
4. 16 priority levels dynamically assigned to interrupt requests
5. Software interrupt generation.
6.3.2. DESCRIPTION:
The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and programmably assigns them into 3 categories, FIQ, vectored IRQ, and non-vectored IRQ.
The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
Fast Interrupt request (FIQ) requests have the highest priority. If more than one request is assigned to FIQ, the VIC ors the requests to produce the FIQ signal to the ARM processor.
The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device.
But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored irqs have the middle priority, but only 16 of the 32 requests can be assigned to this category.
Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored irqs have the lowest priority.
The VIC ors the requests from all the vectored and non-vectored irqs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored irqs are requesting, the VIC provides the address of the highest-priority requesting irqs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored irqs.
The default routine can read another VIC register to see what irqs are active.
All registers in the VIC are word registers. Byte and halfword reads and write are not supported.
Additional information on the Vectored Interrupt Controller is available in the ARM primecell™ Vectored Interrupt Controller (PL190) documentation.
6.3.4.1. Universal Asynchronous Receiver/Transmitter 0:
6.3.4.1.1. Features:
• 16 byte Receive and Transmit fifos
• Register locations conform to ‘550 industry standard
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
• Built-in fractional baud rate generator with autobauding capabilities.
• Mechanism that enables software and hardware flow control implementation
6.3.4.1.4. Architecture:
• The VPB interface provides a communications link between the CPU or host and the UART0.
• The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input.
• The UART0 RX Shift Register (U0RSR) accepts valid characters via RXD0. After a valid character is assembled in the U0RSR, it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface.
• The UART0 transmitter block, U0TX, accepts data written by the CPU or host and buffers the data in the UART0 TX Holding Register FIFO (U0THR).
• The UART0 TX Shift Register (U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the serial output pin, TXD0
• The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by the UART0 TX block.
• The U0BRG clock input source is the VPB clock (PCLK). The main clock is divided down per the divisor specified in the U0DLL and U0DLM registers.
• This divided down clock is a 16x oversample clock, NBAUDOUT.
• The interrupt interface contains registers U0IER and U0IIR. The interrupt interface receives several one clock wide enables from the U0TX and U0RX blocks.
• Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR
6.3.4.2.1. Features:
• UART1 is identical to UART0, with the addition of a modem interface.
• 16 byte Receive and Transmit fifos
• Register locations conform to ‘550 industry standard
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
• Built-in fractional baud rate generator with autobauding capabilities.
• Mechanism that enables software and hardware flow control implementation
• Standard modem interface signals included with flow control (auto-CTS/RTS) fully supported in hardware (LPC2144/6/8 only).
6.3.4.2.4. Architecture:
• The VPB interface provides a communications link between the CPU or host and the UART1.
• The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input.
• The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1.
• After a valid character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface.
• The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register (U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the serial output pin, TXD1.
• The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by the UART1 TX block. The U1BRG clock input source is the VPB clock (PCLK).
• The main clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT The modem interface contains registers U1MCR and U1MSR.
• This interface is responsible for handshaking between a modem peripheral and the UART1
• The interrupt interface contains registers U1IER and U1IIR. The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks.
• Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR.
6.4. Analog-to-Digital Converter (ADC):
6.4.1. Features:
• 10 bit successive approximation analog to digital converter (one in LPC2141/2 and two in LPC2144/6/8).
• Input multiplexing among 6 or 8 pins (ADC0 and ADC1).
• Power-down mode.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Global Start command for both converters (LPC2144/6/8 only).
6.4.2. Description:
Basic clocking for the A/D converters is provided by the VPB clock. A programmable Divider is included in each converter, to scale this clock to the 4.5 mhz (max) clock Needed by the successive approximation process. A fully accurate conversion requires 11 Of these clocks.
6.4.5. Operation:
6.4.5.1. Hardware-triggered conversion:
If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will
Start a conversion when a transition occurs on a selected pin or Timer Match signal. Th choices include conversion on a specified edge of any of 4 Match signals, or conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad
Or the selected Match signal, xored with ADCR bit 27, is used in the edge detection
Logic.
6.4.5.2. Interrupts:
An interrupt request is asserted to the Vectored Interrupt Controller (VIC) when the DONE bit is 1. Software can use the Interrupt Enable bit for the A/D Converter in the VIC to control whether this assertion results in an interrupt. DONE is negated when the ADDR is read.
6.5. Real Time Clock:
6.5.1. Features:
Measures the passage of time to maintain a calendar and clock.
Ultra Low Power design to support battery powered systems
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year
Dedicated 32 khz oscillator or programmable prescaler from VPB clock.
Dedicated power supply pin can be connected to a battery or to the main 3.3 V
6.5.2. Description:
On, and optionally when it is off. It uses little power in Power-down mode. On the LPC2141/2/4/6/8, the RTC can be clocked by a separate 32.768 khz oscillator, or by a programmable prescale divider based on the VPB clock. Also, the RTC is powered by it’s, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device.
6.5.4. Register description:
The RTC includes a number of registers. The address space is split into four sections by functionality. The first eight addresses are the Miscellaneous Register Group(Section 19.4.2).
The second set of eight locations are the Time Counter Group(Section 19.4.12). The third set of eight locations contain the Alarm Register Group(Section 19.4.14). The remaining registers control the Reference Clock Divider. The Real Time Clock includes the register shown in Table 263. Detailed descriptions of the registers follow.
6.5.5. RTC interrupts:
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register (AMR). Interrupts are generated only by the transition into the interrupt state. The ILR Separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the Time counters. If CIIR is enabled for a particular counter, then every time the counter is Incremented an interrupt is generated. The alarm registers allow the user to specify a date And time for an interrupt to be generated. The AMR provides a mechanism to mask alarm Compares. If all nonmasked alarm registers match the value in their corresponding time Counter, then an interrupt is generated. The RTC interrupt can bring the microcontroller out of power-down mode if the RTC is operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is enabled for wakeup and its selected event occurs, XTAL1/2 pins associated oscillator wakeup cycle is started
6.5.7. Interrupt Location Register (ILR - 0xe002 4000):
The Interrupt Location Register is a 2-bit register that specifies which blocks are generating an interrupt (see Table 265). Writing a one to the appropriate bit clears the
6.5.8. Clock Tick Counter Register (CTCR - 0xe002 4004):
The Clock Tick Counter is read only. It can be reset to zero through the Clock Control Register (CCR). The CTC consists of the bits of the clock divider counter
6.6. LINEAR KEYPAD:
This section basically consists of a Linear Keypad. Basically a Keypad can be classified into 2 categories. One is Linear Keypad and the other is Matrix keypad.
1. Matrix Keypad.
2. Linear Keypad.
6.6.1 Matrix Keypad:
This Keypad got keys arranged in the form of Rows and Columns. That is why the name Matrix Keypad. According to this keypad, In order to find the key being pressed the keypad need to be scanned by making rows as i/p and columns as output or vice versa.
This Keypad is used in places where one needs to connect more no. Of keys with less no Of data lines.
6.6.2. Linear Keypad:
This Keypad got ‘n’ no. Of keys connected to ‘n’ data lines of microcontroller. This Keypad is used in places where one needs to connect less no. Of keys. Generally, in Linear Keypads one end of the switch is connected to Microcontroller (Configured as i/p) and other end of the switch is connected to the common ground. So whenever a key of Linear Keypad is pressed the logic on the microcontroller pin will go LOW.
Here in this project, a linear keypad is used with switches connected in a serial manner. Linear keypad is used in this project because it takes less no. Of port pins. The Linear Keypad with 4 Keys is shown below.
6.7. DIFFERENT TYPES OF MOTORS:
Figure 1
In figure1 different types of motors is there in this we are using FF-N30SA-1555 motor i.e. Mentioned in the below.
6.7.1. CHINA MOTOR:
Fig 6.7: China motor
Flat Type DC motor for Audio and Visual Equipments, toys and aviation aerial models, household appliances.
Model: FF-N30SA-1555
Flat type diameter: 12mm (D) x 19.8mm (L)
Voltage (V): 3V
Operation voltage: 2-5V
No load speed: 20800rpm current: 0.10A,
At maximum efficiency speed: 17240rpm, current: 0.434A, torque: 28gcm
Stall torque: 28gcm
6.7.2. H-BRIDGE:
DC motors are typically controlled by using a transistor configuration called an "H-bridge". This consists of a minimum of four mechanical or solid-state switches, such as two NPN and two PNP transistors. One NPN and one PNP transistor are activated at a time. Both NPN and PNP transistors can be activated to cause a short across the motor terminals, which can be useful for slowing down the motor from the back EMF it creates.
6.7.2.1. Basic Theory:
H-bridge sometimes called a "full bridge" the H-bridge is so named because it has four switching elements at the "corners" of the H and the motor forms the cross bar.
The key fact to note is that there are, in theory, four switching elements within the bridge. These four elements are often called, high side left, high side right, low side right, and low side left (when traversing in clockwise order).
The switches are turned on in pairs, either high left and lower right, or lower left and high right, but never both switches on the same "side" of the bridge. If both switches on one side of a bridge are turned on it creates a short circuit between the battery plus and battery minus terminals. If the bridge is sufficiently powerful it will absorb that load and your batteries will simply drain quickly. Usually however the switches in question melt.
To power the motor, you turn on two switches that are diagonally opposed. In the picture to the right, imagine that the high side left and low side right switches are turned on.
The current flows and the motor begins to turn in a "positive" direction. Turn on the high side right and low side left switches, then Current flows the other direction through the motor and the motor turns in the opposite direction.
Actually it is just that simple, the tricky part comes in when you decide what to use for switches. Anything that can carry a current will work, from four SPST switches, one DPDT switch, relays, transistors, to enhancement mode power mosfets.
One more topic in the basic theory section, quadrants. If each switch can be controlled independently then you can do some interesting things with the bridge, some folks call such a bridge a "four quadrant device" (4QD get it?). If you built it out of a single DPDT relay, you can really only control forward or reverse. You can build a small truth table that tells you for each of the switch's states, what the bridge will do. As each switch has one of two states, and there are four switches, there are 16 possible states. However, since any state that turns both switches on one side on is "bad" (smoke issues forth: P), there are in fact only four useful states (the four quadrants) where the transistors are turned on.
High Side Left High Side Right Low Side Left Low Side Right Quadrant Description
On Off Off On Forward Running
Off On On Off Backward Running
On On Off Off Braking
Off Off On On Braking
The last two rows describe a maneuver where you "short circuit" the motor which causes the motors generator effect to work against itself. The turning motor generates a voltage which tries to force the motor to turn the opposite direction. This causes the motor to rapidly stop spinning and is called "braking" on a lot of H-bridge designs.
Of course there is also the state where all the transistors are turned off. In this case the motor coasts freely if it was spinning and does nothing if it was doing nothing.
6.7.2.2. Implementation:
6.7.2.2.1 Using Relays:
A simple implementation of an H Bridge using four SPST relays is shown. Terminal A is High Side Left, Terminal B is High Side Right, Terminal C is Low Side Left and Terminal D is Low Side Right. The logic followed is according to the table above.
Warning: Never turn on A and C or B and D at the same time. This will lead to a short circuit of the battery and will lead to failure of the relays due to the large current.
6.7.2.2.2. Using Transistors:
We can better control our motor by using transistors or Field Effect Transistors (fets). Most of what we have discussed about the relays H-Bridge is true of these circuits. See the diagram showing how they are connected. You should add diodes across the transistors to catch the back voltage that is generated by the motor's coil when the power is switched on and off. This fly back voltage can be many times higher than the supply voltage!
For information on building an H-Bridge using Transistors, have a look here.
Warning: If you don't use diodes, you could burn out your transistors. Also the same warning as in the diode case. Don't turn on A and C or B and D at the same time.
Transistors, being a semiconductor device, will have some resistance, which causes them to get hot when conducting much current. This is called not being able to sink or source very much power, i.e.: Not able to provide much current from ground or from plus voltage.
Mosfets are much more efficient, they can provide much more current and not get as hot. They usually have the fly back diodes built in so you don't need the diodes anymore. This helps guard against fly back voltage frying your ics.
To use Mosfets in an H-Bridge, you need P-Channel Mosfets on top because they can "source" power, and N-Channel Mosfets on the bottom because then can "sink" power.
It is important that the four quadrants of the H-Bridge circuits be turned on and off properly. When there is a path between the positive and ground side of the H-Bridge, other than through the motor, a condition exists called "shoot through". This is basically a direct short of the power supply and can cause semiconductors to become ballistic, in circuits with large currents flowing. There are H-bridge chips available that are much easier, and safer, to use than designing your own H-Bridge circuit.
6.7.2.2.3. Using H-Bridge Devices:
The L293 has 2 H-Bridges (actually 4 Half H-Bridges), can provide about 1 amp to each and occasional peak loads to 2 amps.
The L298 has 2 h-bridges on board, can handle 1amp and peak current draws to about 3amps. The LMD18200 has one h-bridge on board, can handle about 2 or 3 amps and can handle a peak of about 6 amps. There are several more commercially designed H-Bridge chips as well.
Once a Half H-bridge is enabled, it truth table is as follows:
INPUT
A OUTPUT
Y
L L
H H
So you just give a High level when you want to turn the Half H-Bridge on and Low level when you want to turn it off. When the Half H-Bridge is on, the voltage at the output is equal to Vcc2.If you want to make a Full H-Bridge, you connect the motor (or the load) between the outputs of two Half H-Bridges and the inputs will be the two inputs of the Half H-Bridges.