31-01-2013, 04:37 PM
A Low Power Booth Multiplier Based on Operand Swapping in Instruction Level
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ABSTRACT
We present a new low-power modied Booth algorithm with multiplier and multiplicand swapping
based on a new power estimation model in instruction level. The estimation model considers a new
recoding weight with the inter-instruction eects. The proposed algorithm in this paper results in a
power reduction of 8 % on the average of 8 % of instances, compared with the previous result. The
new low-power modied Booth multiplier has an important application to Digital Signal Processing
performing many multiplication iterations.
INTRODUCTION
A multiplier plays an important role in various digital
systems such as computer, process controller and signal
processor. Designing fast and low power multipliers
has long been a great theoretical and practical interest
for computer scientists and engineers. Various multiplication
algorithms have been proposed, and many researchers
have tried to develop high speed multiplication
algorithms suitable for VLSI implementation [3,4].
The shift-and-add algorithm is a familiar multiplication
method. Parallel multipliers based on the algorithm,
i:e:, array multipliers, have been widely used, and some
of them are being implemented on commercial LSI chips.
This type of multiplier has a regular cellular array structure
of one type of basic cell and is very suitable for
VLSI implementation. However, it does not operate
fast enough for longer operands because its computation
time is linearly proportional to the word length of
operands. In order to achieve high-speed multiplication,
multiplication algorithms using parallel counters, such
as the modied Booth algorithm [3,7] and the Wallace
tree [4], have been proposed, and some multipliers based
on the algorithms have been implemented for practical
use. This type of multiplier operates much faster than an
array multiplier for longer operands because its computation
time is proportional to the logarithm of the word
length of operands.
MODIFIED BOOTH MULTIPLIER
Review the previous modied Booth
algorithm that has been widely used [3]. It is based on
the encoding the two's complements multiplier in order
to reduce the number of partial products to be added [1].
This makes the multiplier faster and consumes less
hardware area. The modied Booth algorithms using
radix-4 is based on the partitioning of the multiplier
into overlapping groups of 3-bits, as multibit recoding
[2], and each group is decoded to generate the correct
partial product.
POWER ANALYSIS IN INSTRUCTION
LEVEL
As a minimum power estimation, it is necessary to determine
the base cost of individual instructions. Base
cost refers to the portion of the power dissipation of an
instruction that is independent of the prior state of the
processor. Base costs for each instruction are not always
adequate for a precise software power estimate. There
are other energy costs that can be directly attributed to
localized processor state changes resulting from the execution
of a pair of instructions. These costs are referred
to as circuit state or inter-operation eects. In other
words, circuit state eect is the energy dissipated as a
result of the processor switching from execution of one
type of instruction to another.
INSTRUCTION ORDERING AND
SWAPPING FOR LOW POWER
In this section, we present the operand swapping for
low power associated with the base cost and circuit state
eects. Operand swapping means to swap two operands
to minimize the switching activity associated with the
operation. For example, the number of additions, shifts
and complements performed in the modied Booth multiplier
depends on the bit pattern of the second operand
(i:e; multiplier) [5]. The number of additions, shifts and
complements required is dened as the recoding weight
of the second operand. If an operand is known to have a
higher recoding weight, then the operand is placed in the
rst operand position. If an operand is known to have a
lower recoding weight, then the operand is placed in the
second position. However [6], revealed that the recoding
weight estimation is not accurate and has 5 % errors [6].
does not consider the circuit state eects. Therefore, we
present a new model of the recoding weight, considering
the circuit state eects of instructions.
CONCLUSIONS
In this paper we proposed a new low-power modi-
ed Booth algorithm based on operand swapping with a
new power estimation in instruction level. The proposed
modied Booth multiplier uses a new recoding weight
measure considering the circuit state eects. The new
low-power modied Booth multiplier can be eectively
used for Digital Signal Processing (DSP) applications.
That is, in DSP applications, we can incorporate the
register allocation scheme into our algorithm to further
minimize the switching activity in shared registers.