26-07-2012, 01:02 PM
asynchronous circuit design:specification and synthesis
asynchronous circuit design.ppt (Size: 282.5 KB / Downloads: 98)
Synchronous communication
Clock edges determine the time instants where data must be sampled
Data wires may glitch between clock edges (set-up/hold times must be satisfied)
Data are transmitted at a fixed rate(clock frequency)
Bundled data
Validity signal
Similar to an aperiodic local clock
n-bit data communication requires n+1 wires
Data wires may glitch when no valid
Signaling protocols
level sensitive (latch)
transition sensitive (register): 2-phase / 4-phase
Asynchronous modules
Signaling protocol:reqin+ start+ [computation] done+ reqout+ ackout+ ackin+reqin- start- [reset] done- reqout- ackout- ackin-(more concurrency is also possible, e.g. by overlapping the return-to-zero phase of step i-1 with the evaluation phase of step i)
Motivation
Low power
Automatic clock gating
Electromagnetic compatibility
No peak currents around clock edges
Robustness
High immunity to technology and environment variations (in-die variations, temperature, power supply, ...)