Recent years have seen rapid development in the area of the wireless network. So far, wireless networks have focused on high-speed and long-range applications. Zigbee technology was developed for Wireless Personal Area Networks (WPAN), targeting military and control applications with low data rates and low power consumption. Zigbee is a standard that defines the set of communication protocols for short-range wireless data networks. Zigbee-based wireless devices operate in the 868 MHz, 915 MHz and 2.4 GHz frequency bands. The maximum data rate is 250K bits per second. Zigbee is primarily for battery applications where low data rates, low cost and battery life are the primary requirements. This article explores the design of Verilog for several blocks in the Zigbee Transmitter architecture for an acknowledgment frame. The digital word has had a dramatic impact on our society. The development of digital solutions has been possible due to the good design of digital systems and modeling techniques. New developments have been made and introduced VLSI in order to reduce the size of the architecture, to improve the speed of operation, improvements in the predictability of circuit behavior. The Zigbee Digital Transmitter consists of cyclic redundancy control, bit-to-symbol block, symbol-to-chip block, modulator, and pulse configuration blocker. The work here is to show how we can design Zigbee transmitter with its specifications using Verilog with fewer number of slices and Look up tables (LUTs).