02-02-2013, 10:22 AM
"distributed packet buffers for high bandwidth switches and routers":
i am final year student.i want clear explanation of abstract and basepaper of the above ieee project.
the abstract of my topic is:
Abstract—High-speed routers rely on well-designed packet buffers that support multiple queues, provide large capacity and short
response times. Some researchers suggested combined SRAM/DRAM hierarchical buffer architectures to meet these challenges.
However, these architectures suffer from either large SRAM requirement or high time-complexity in the memory management. In this
paper, we present scalable, efficient, and novel distributed packet buffer architecture. Two fundamental issues need to be addressed
to make this architecture feasible: 1) how to minimize the overhead of an individual packet buffer; and 2) how to design scalable packet
buffers using independent buffer subsystems. We address these issues by first designing an efficient compact buffer that reduces the
SRAM size requirement by (k 1Þ=k. Then, we introduce a feasible way of coordinating multiple subsystems with a load-balancing
algorithm that maximizes the overall system performance. Both theoretical analysis and experimental results demonstrate that our
load-balancing algorithm and the distributed packet buffer architecture can easily scale to meet the buffering needs of high bandwidth
links and satisfy the requirements of scale and support for multiple queues.