As the transistors decrease in size, more and more of them can be accommodated in a single die, thus increasing the computational capacities of the chips. However, the transistors may not be much smaller than their current size. The quantum cellular automata approach (QCA) represents one of the possible solutions to overcome this physical limit, although the design of logical modules in QCA is not always simple. In this brief, we propose a new adder that surpasses all the avant-garde competitors and achieves the best compromise of area delay. The above advantages are obtained by using a total area similar to the cheaper designs known in the literature. The 64-bit version of the new adder covers more than 18.72 μ2 active area and shows a delay of only nine clock cycles, ie only 36 clock phases.