i am ph.d student who is looking for approximate adder and multipliers code . i am keen to work on this area for my ph.d . so i want to explore this area first
Abstract-
The addition of two binary numbers is the most
fundamental and widely used arithmetic operation. This
operation is used in microprocessors, digital signal processors,
data processing application specific integrated circuits and many
more. There are many adders designed till now. ETA is one such
efficient adder which speeds up binary addition. ETA is the Error
Tolerant Adder which consumes less power and delay. Design of
ETA is done using backend tool under real time simulation
conditions. This paper compares the performance of the ETA in
terms of accuracy, delay and power consumption with that of
conventional adders.
There is a huge improvement in the power and speed when
we use an ETA. For increasing the speed and decreasing the
power dissipation, we use the logic that in an adder circuit the
delay appears mainly because of the carry propagation and also
there is a lot of power dissipation. So we try to eliminate this
carry propagation by dividing the addition of two binary numbers
into two parts namely accurate part and inaccurate part as shown
below. The 4 MSB bits of both the numbers are the accurate part
and the 4 LSB bits are the inaccurate part. In the accurate part the
addition is performed in a conventional way from right to left
starting from the demarcation line because the higher order bits
play a greater role in the accuracy. In the inaccurate part, the
addition is performed from left to right strarting from the
demarcation line. When two 0s are there or a 0 and a 1 is there,
the addition proceeds conventionally. As soon as two 1s in the
input bits are seen, the checking stops and from this point
onwards all the bits are set to 1 as shown below. This method is
adopted in order to eliminate the time required for carry
propagation and also to reduce the power consumption.