10-11-2012, 05:37 PM
Power Reduction In Single Phase Clock Multiband Flexible Divider Using 180 nm Technology
Power Reduction In Single Phase.pptx (Size: 276.42 KB / Downloads: 126)
INTRODUTION
The demand for lower cost, lower power, and multiband RF circuits increased in conjunction with need of higher level of integration.
The proposed system based on pulse-swallow topology and is implemented using a 0.18-µm CMOS technology.
The multiband divider consists of a proposed wideband multi modulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter .
The expected outcome of the proposed multiband flexible divider is silicon consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.
EXISTING SYSTEM
A dual-modulus prescaler usually consists of a divide-by-2/3 (or 4/5) unit followed by several asynchronous divide-by-2 units.
The operation of the divide-by-2/3 unit at the highest input frequency makes the prescaler design complicated.
To achieve the two different division ratios, D flip-flops (DFFs) and additional logic gates, which reduce the operating frequency by introducing an additional propagation delay and the power consumption is also high.
DYNAMIC LOGIC MULTIBAND FLEXIBLE DIVIDER:
The multimodal’s prescaler consists of the wideband 2/3 prescaler , four asynchronous TSPC divide-by-2 circuits and combinational logic circuits to achieve multiple division ratios.
The 6-bit s-counter consists of six asynchronous loadable bit-cells, a NOR-embedded DFF and additional logic gates.
To allow it to be programmable from 0 to 31 for low-frequency band and from 0 to 47 for the high-frequency band.