03-01-2013, 04:27 PM
Computer Organization
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Introduction
There are two types of sequential circuits:
synchronous: outputs change only at specific time
asynchronous: outputs change at any time
Multivibrator: a class of sequential circuits. They can be:
bistable (2 stable states)
monostable or one-shot (1 stable state)
astable (no stable state)
Bistable logic devices: latches and flip-flops.
Latches and flip-flops differ in the method used for changing their state.
S-R Latch
Complementary outputs: Q and Q'.
When Q is HIGH, the latch is in SET state.
When Q is LOW, the latch is in RESET state.
For active-HIGH input S-R latch (also known as NOR gate latch),
R=HIGH (and S=LOW) a RESET state
S=HIGH (and R=LOW) a SET state
both inputs LOW a no change
both inputs HIGH a Q and Q' both LOW (invalid)!
Latch Circuits: Not Suitable
Latch circuits are not suitable in synchronous logic circuits.
When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.
The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change.
This leads us to the edge-triggered memory elements called flip-flops.
Edge-Triggered Flip-flops
Flip-flops: synchronous bistable devices
Output changes state at a specified point on a triggering input called the clock.
Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.
Asynchronous Inputs
S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse.
Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)]
When PRE=HIGH, Q is immediately set to HIGH.
When CLR=HIGH, Q is immediately cleared to LOW.
Flip-flop in normal operation mode when both PRE and CLR are LOW.