19-08-2014, 03:05 PM
DESIGN AND IMPLEMENTATION OF A 16 BIT RISC
MICROCONTROLLER”
DESIGN AND IMPLEMENTATION.pdf (Size: 1.41 MB / Downloads: 123)
ABSTRACT
Microcontrollers have traditionally been designed around two approaches: Complex
Instruction Set Computer (CISC) and Reduced Instruction Set Computer
(RISC).RISC is a microprocessor that is designed to perform a smaller number of
types of computer instructions so that it can operate at a higher speed. We used RISC
design approach to design “FPGA Implementation of RISC Controller”.
A description of high performance 16-bit Microcontroller based on the Reduced
Instruction Set Computer (RISC) design concept is presented in this report. The
objective is to design a general-purpose RISC Microcontroller, modular design and
bottom-up implementation of this RISC microcontroller implemented on a Field
Programmable Gate Arrays (FPGAs). Microcontroller implemented the arithmetic
logic unit, shifter, comparators, multiplier, divider and control unit. Microcontroller
includes 16-bit register file having a dedicated arithmetic logic unit (ALU), In
addition to a general purpose 16-bit arithmetic logic unit. The arithmetic logic unit
provides certain arithmetic and logical functions. The RISC processor has the Harvard
architecture, which uses separate memory access ports for program and data.
The microcontroller can execute 54 instructions such as add, subtract, multiply,
divide, load and store. Each instruction will take a three basic step to execute the
instruction fetch, decode and execute. Hardwired control implementation is used in
RISC microcontroller to achieve the single clock cycle per instruction. Thus, the time
required to execute each instruction can be shortened and the number of cycles
(machine cycle-T state) reduced.
The 16-bit RISC microcontroller has been designed with VHDL, synthesized
using Xilinx ISE 7.1i, simulated using ModelSim simulator, and then implemented on
Xilinx Spartan 2E FPGA that has 8MHz clock oscillator.
Introduction:
Increasing performance and gate capacity of recent FPGA devices permits complex logic
systems to be implemented on a single programmable device. Such a growing complexity
demands design approaches, which can cope with designs containing hundreds of
thousands of logic gates, memories, high-speed interfaces, and other high-performance
components. The RISC Processor works on reduced number of Instructions, fixed
instruction length, more general-purpose registers, load-store architecture and simplified
addressing modes which makes individual instructions execute faster, achieve a net gain
in performance and an overall simpler design with less silicon consumption as compared
to CISC.[14]
The premise of the project was to create FPGA (Field Programmable Gate Array)
implementation of RISC (Reduced Instruction Set Computer) controller via VHDL
(Very high speed integrated circuit Hardware Description Language) design. The idea of
the design was to start with a basic 16-bit microcontroller that could easily be explained
to include the additional special function. For testing and demonstration purpose the
design can be loaded into a Field Programmable Gate array, or FPGA, which is
essentially a temporary imitation of the real chip. Although not perfect an FPGA allows
an engineer to test a design in minutes instead of months (it takes several months to get a
chip fabricates but an FPGA loads in seconds). Due to VLSI chips are created there is still
a small chance a fabricated chip will fail, even if tests successfully on an FPGA.
Introduction:
Increasing performance and gate capacity of recent FPGA devices permits complex logic
systems to be implemented on a single programmable device. Such a growing complexity
demands design approaches, which can cope with designs containing hundreds of
thousands of logic gates, memories, high-speed interfaces, and other high-performance
components. The RISC Processor works on reduced number of Instructions, fixed
instruction length, more general-purpose registers, load-store architecture and simplified
addressing modes which makes individual instructions execute faster, achieve a net gain
in performance and an overall simpler design with less silicon consumption as compared
to CISC.[14]
The premise of the project was to create FPGA (Field Programmable Gate Array)
implementation of RISC (Reduced Instruction Set Computer) controller via VHDL
(Very high speed integrated circuit Hardware Description Language) design. The idea of
the design was to start with a basic 16-bit microcontroller that could easily be explained
to include the additional special function. For testing and demonstration purpose the
design can be loaded into a Field Programmable Gate array, or FPGA, which is
essentially a temporary imitation of the real chip. Although not perfect an FPGA allows
an engineer to test a design in minutes instead of months (it takes several months to get a
chip fabricates but an FPGA loads in seconds). Due to VLSI chips are created there is still
a small chance a fabricated chip will fail, even if tests successfully on an FPGA.
PURPOSE OF THE THESIS
The main purpose of the thesis is the implementation of RISC controller in an FPGA
and reducing the instruction’s execution time for machine cycles. The implementation
was done using a bottom-up approach. The basic hardware blocks like adders, shift
registers; multiplier divider and comparators were designed. Later, these blocks were
used to form ALU, RAM, and instruction decoder. Finally, in the top-level module,
these blocks were connected to form a functional microcontroller. The RISC
processor has the Harvard architecture, which uses separate memory access ports for
program and data. Hardwired control approach is best suited for control unit of RISC
processor because very few control signals needs to be generated for smaller set of
instructions.
MICROCONTROLLER
A controller is used to control some process. At one time, controllers were built
exclusively from logic components, and were usually large, heavy boxes. Later on,
microprocessors were used and the entire controller could fit on a small circuit board.
This is still common– one can find many controllers powered by one of the many
common microprocessors (including Zilog Z80, Intel 8088, Motorola 6809, and
others). As the process of miniaturization continued, all of the components needed for
a controller were built right onto one chip. A one chip computer, or microcontroller
was born.
CONCLUSION AND
FUTURE SCOPE
The section includes conclusions drawn on the basis of functional simulation results
as well as implementation of the design on FPGA.
A 16-bit RISC microcontroller is designed using VHDL, and also implemented on
Xilinx Spartan-2E Evaluation board. Simulation and implementation tools used are
Xilinx ISE and Modelsim. There were some limitations encountered when the
program uploading and testing due to the evaluation board limitations. Multiplication
operation could be implemented for the cases when the resulting number doesn’t
exceed 16-bit. Division operation is achieved only for the cases when resulting
numbers are without residue.
Functional verification shows the accurate results for instruction set add, subtract,
compare, shift-left, shift-right, rotate-left, rotate-right, AND, OR, NOT operations.
The developed microcontroller module functions with simple control signals. The
developed module is functionally built using structural approach in VHDL. Therefore,
this microcontroller can be used as a module in complex board level designs. Also,
because of the modular design and bottom-up implementation of this microcontroller,
the VHDL code can easily be expanded to develop higher order microcontroller
without making extensive changes. This VHDL program will be compatible with any
other VHDL system that is compliant with either IEEE Standard 1076-1987 or 1076-
1993.
The microcontroller can execute 54 instructions such as add, subtract, multiply,
divide, load and store. Each instruction will take a three basic step to execute the
instruction fetch, decode and execute. Hardwired control implementation is used in
RISC microcontroller to achieve the single clock cycle per instruction. Thus, the time
required to execute each instruction can be shortened and the number of cycles
(machine cycle-T state) reduced.
Future work will be added by increasing the number of instructions and make a
pipelined design with less clock cycles per instruction and more improvement can be
added in the future work. There are many more extra features available in the RISC
microcontroller family, such as the UART serial interface, SPI serial interface, the 16-
bit timer (with output compare and input capture), e