26-07-2012, 04:44 PM
scalable architecture
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ABSTRACT
This paper presents a scalable architecture for developing custom floating point multipliers targeted to FPGA synthesis. An evaluation of several multipliers of different typical sizes synthesized for testing purposes is also presented, highlighting the strengths and limitations of this approach in the creation of custom floating point units.
INTRODUCTION
The reconfigurability and programmability of Field Programmable Gate Arrays (FPGAs) make them attractive tools for implementing digital signal processing (DSP) applications. However, DSP applications are arithmetic intensive tasks, requiring in most cases floating point operations to be performed as part of the application itself.This creates a necessity for some off-the-shelf floating point units which could be used in these applications without
deviating the designer’s attention from the main problem being solved. A number of custom implementations of fixed and floating point units have been reported for several FPGA architectures most of them aimed at solving specific problems.
This paper presents the implementation of a general purpose, scalable architecture used to build floating point multipliers on FPGAs. What makes this implementation different and general purpose is its flexibility in accepting as a user parameter the operand size of the unit about to be synthesized. This feature makes our implementation a very convenient tool for rapid application prototyping. The next section explains the format used to represent the FP numbers in the implementation. The multiplier structure, along with the approach for writing the scalable circuit description are explained in section three. Section four presents the results of synthesizing five different sizes of multipliers using the developed tool. This section also includes a comparison of units generated with our tool against similar units previously reported, allowing us to evaluate their efficiency..
Operand Format
In order to facilitate the integration of the multipliers into the diverse applications that might require them, we decided to follow as closely as possible the representation format of the IEEE 754 standard for single-precision numbers. The selection of this format allowed us not only to adhere to a well known representation format, but also to take advantage of some features of the standard. These features include the reduction of the representation error, the 4 ability of representing the inverse of any representable number without causing either overflow or underflow errors, and giving support to infinity values in operations. The number of bits allocated for a number represented in this format is divided into three main fields, as illustrated
in Figure 1. A brief description of these three fields follows.
i) The mantissa f, held in the rightmost field of the operand, is represented as an m-bit unsigned-magnitude number, plus an implicit hidden +1 bit. Mantissa values are normalized to reduce the number of leading zeros in the field, increasing the precision. Once normalized and augmented, the resulting value lies in the range.
ii) The sign bit S, held in the leftmost position of the n-bit word, is set to one to represent negative mantissas, or to zero otherwise.
iii) The exponent E, an e-bit wide field, uses an excess encoding (bias) to represent the actual exponent value. This allows, among other things, to represent all numbers in the format and their inverses without causing overflow/underflow conditions.
Some additional features supported by the 754 standard, and adopted in our representation include: a zero value is represented by E=0, f=0; an infinity value () is represented as E=1..1, f=1..1 (all ones in both fields), and sign bit accordingly. Overflow and underflow indications are provided through two status bits. Denormalized numbers and NaN representations are not supported in this implementation. The value of a floating point number F in this format can be obtained as follows:
F = (–1)^s* 1. f * 2^E – bias
Multiplier Structure
The multiplication of two floating point numbers involves three steps: adding the exponents, multiplying the mantissas, and operating on the signs of the values. The exponent addition is performed as an integer operation, requiring an adjustment in the result to subtract the redundant exponent bias. The mantissa multiplication is also performed as an integer operation, from which only the most significant m bits are taken. The sign of the result is computed by performing an exclusive-or operation on the signs of the input values. A postnormalization step might be required if the resulting product is equal to or larger than two. This step is commonly achieved by shifting its mantissa one position to the right, and adding one to the resulting exponent.
In addition, the bounds of the results must be checked in order to detect possible overflow/underflow conditions which may arise during the process. In order to perform the above sequence of operations within an acceptable time frame, the multiplier structure is organized as a three-stage pipeline. This arrangement allows the system to produce one result every clock cycle, after the first three values are entered into the unit. Figure 2 shows a block diagram with the structure of the multiplier pipeline. Each stage in this pipeline performs one or more simultaneous operations, as described below.
performs the addition of the exponents, the multiplication of the mantissas, and the exclusive-or of the signs.
- takes these results as inputs, removing the redundant bias in the exponent, postnormalizing the resulting mantissa, and passing the sign. Stage 3 is devoted to rounding and representing the result according the overflow/underflow conditions which might be generated during the process.