22-07-2012, 02:43 PM
may you provide me the coding for accumulator based 3-weight pattern generation system?and suggest idea in further improvement/future enhancements in it..
22-07-2012, 02:43 PM
may you provide me the coding for accumulator based 3-weight pattern generation system?and suggest idea in further improvement/future enhancements in it..
14-08-2012, 10:32 AM
POWER POINT PRESENTATION ON ACCUMULATOR BASED 3 WEIGHT PATTERN GENERATION
18-08-2012, 06:35 PM
KINDLY LET ME KNOW WHAT IS ACCUMULATOR BASED PATTERN GENERATOR
13-09-2012, 12:23 PM
ACCUMULATOR BASED 3-WEIGHT PATTERN GENERATION
ITVL01 FUTURE ENHANCEMENT1.docx (Size: 400.44 KB / Downloads: 51) ABSTRACT: A heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuit. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault- detecting patterns. Here, we develop simple way of generating a test set which simultaneously providing a test pattern generation circuit of c880 with respect to all inputs subset to logic circuit up to certain size and it is shown that such a test set may be formed with vectors of a particular set of weights.
21-11-2012, 02:45 PM
ACCUMULATOR BASED 3-WEIGHT PATTERN GENERATIONINTRODUCTION INTRODUCTION Pseudorandom built-in self test (BIST) generators have been widely utilized to test integrated circuits and systems. The arsenal of pseudorandom generators includes, among others, linear feedback shift registers (LFSRs), cellular automata, and accumulators driven by a constant value. For circuits with hard-to-detect faults, a large number of random patterns have to be generated before high fault coverage is achieved. Therefore, weighted pseudorandom techniques have been proposed where inputs are biased by changing the probability of a “0” or a “1” on a given input from 0.5 (for pure pseudorandom tests) to some other value. In order to minimize the hardware implementation cost, other schemes based on multiple weight assignments utilized weights 0, 1, and 0.5. SCOPE OF THE PROJECT Current VLSI circuits, e.g., data path architectures, or digital signal processing chips commonly contain arithmetic modules [accumulators or arithmetic logic units (ALUs)]. This has fired the idea of arithmetic BIST (ABIST). The basic idea of ABIST is to utilize accumulators for built-in testing (compression of the CUT responses, or generation of test patterns) and has been shown to result in low hardware overhead and low impact on the circuit normal operating speed. LITERATURE SURVEY The cellular automata-logic-block-observation (CALBO) circuits of this paper are anticipated to improve upon conventional design for testability circuitry such as BILBO as a direct consequence of reduced cross correlation between the bit streams which are used as inputs to the logic unit under test. Certain types of circuit faults are undetectable using the correlated bit streams produced by the conventional linear-feedback-shift-register (LFSR). In addition it is noted that CA implementations exhibit data compression properties similar to the LFSR and that they display locality and topological regularity, important attributes for a VLSI implementation. An important feature still to be fully investigated is the possibility that some CA’s may be able to generate weighted pseudorandom test patterns. Distributed Generation of Weighted Random Patterns - Jacob Savir A new weighted random pattern (WRP) design for testability (DFT) is described where the shift register latches (SRLs) distributed throughout the chip are modified so that they can generate biased pseudo-random patterns upon demand. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. FUTURE ENHANCEMENT DESCRIPTION According to this paper, our future work is to check the performance of the bench mark circuit c880. The Bench mark circuit consists of 60 inputs, 26 outputs, and 383 gates. It’s an 8-bit ALU with high level model. The core of this 8-bit ALU is an 8-bit 74283-style adder. To analyze the C880 we have to modify our proposed test pattern architecture. Because C880 consist of 60 inputs but our proposed testing hardware provides of demo test pattern only. |
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