Implementation of an improved 8-bit Vedic multiplier in terms of propagation delay compared to conventional multiplier such as array multiplier, Braun multiplier, modified cabin multiplier and Wallace tree multiplier. In our design we have used the 8-bit barrel changer which requires only one clock cycle for the number of changes. The design is implemented and verified using FPGA and ISE Simulator. The kernel was implemented in Xilinx Spartan-6 family xc6s1x75T-3-fgg676 FPGA. The propagation delay comparison was also extracted from the synthesis report and the static timing report. The design could achieve a propagation delay of 6.781ns using the bar shifter in the base selection module and the multiplier.
Currently the speed of the multipliers is limited by the speed of the summers used for the partial addition of product. The partial addition of the product to the Vedic multiplier is performed using the carry-skip technique. An 8-bit multiplier is performed using a 4-bit multiplier and modified ripple load inverters. In the proposed design we have reduced the number of logic levels, thus reducing the logical delay. The architecture simulation is performed with Xilinx ISIM and is synthesized using Xilinx XST. The results indicate a 13.65% increase in velocity when compared to the normal Vedic multiplier.
A multiplier is a vital element in almost all processors and contributes significantly to the total power utilization of the system. The point of the novel is the efficient use of the Vedic algorithm (sutras) which reduces the number of computational steps considerably compared to any conventional method. The scheme for this multiplier is designed using the Tanner tool. The design is verified in T-SPICE using a 180 nm CMOS technology model library file. The analysis is done for voltage ranges from 2.5V to 5V, to simulate the design. A CMOS multiplier is proposed, with low power consumption and high linearity. The results show that the proposed multiplier consumes 75% less power compared to the previous door level analysis. The central area of the proposed multiplier is 720 um2. Paper presents a methodical design methodology for this improved performance digital multiplier based on Vedic math.