Introduction
Viterbi decoder is an important block in any CDMA modem. CDMA systems being interference based use forward error correction schemes like convolution encoding to increase cell capacity. The Viterbi Algorithm may be viewed as a solution to the problem of maximum a posteriori probability estimation of the state sequence of a finite-state discrete-time Markov process observed in memory less noise. A tutorial on Viterbi algorithm can be found in . One of the main blocks of a modem used during forward-link demodulation is a Viterbi decoder. A normal Viterbi decoder for a constraint length of 9 (256 states) uses more than 15 kb of memory and can occupy as high as 1/3 of the modem chip area. Our aim was to design a 19.2 kbps, 256 state Viterbi decoder with the added capability of catering to higher input data rates. To the best of our knowledge none of the literature discusses Viterbi decoder implementation based on high level synthesis targeted for Field Programmable Gate Arrays (FPGAs). This has been the focus in the present paper. Several important design issues, such as, organization of a path memory, decision memory, the decision memory reading techniques, and the clocking mechanism have not been made available due to the proprietary nature of the system implementation. For example, some of the implementations use twos' complement representation for the path metrics. However, this can only be achieved at the cost of an important metric used for input bit sequence synchronization. We aimed at retaining this bit-synchronization metric, even though it made the normalization of the path metrics essential.