15-05-2014, 11:05 AM
OMAP5910 Dual-Core Processor
Introduction
This section describes the main features of the OMAP5910 device, lists the terminal assignments, and
describes the function of each terminal. This data manual also provides a detailed description section,
electrical specifications, parameter measurement information, and mechanical data about the available
packaging.
Description
The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application
processing needs of next-generation embedded devices.
The OMAPTM platform enables OEMs and ODMs to quickly bring to market devices featuring rich user
interfaces, high processing performance, and long battery life through the maximum flexibility of a fully
integrated mixed processor solution.
The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a
TMS320C55x DSP core and a high-performance TI925T ARM core.
The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as
well as the Texas Instruments (TI) DSP/BIOSTM software kernel foundation, and is available in a 289-ball
MicroStar BGATM package.
DSP Tools Support
The 55x DSP core is supported by the industry’s leading eXpressDSPTM software environment including the
Code Composer StudioTM integrated development environment, DSP/BIOS software kernel foundation, the
TMS320TM DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio
features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange
(RTDXTM), XDS510TM emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable
real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a
preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead.
The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of
algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’
extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions
to customers.
DSP I/O Space Memory Map
The DSP I/O space is a separate address space from the data/program memory space. The I/O space is
accessed via the DSP’s port instructions. The Public and Shared peripheral registers are also accessible by
the MPU through the MPUI (MPU Interface) port. The DSP I/O space is accessed using 16-bit word
addresses. The following tables specify the DSP base addresses where each set of registers is accessed.
All accesses to these registers must utilize the appropriate access width as indicated in the tables. Accessing
registers with the incorrect access width may cause unexpected results including a TI Peripheral Bus (TIPB)
bus error and associated TIPB interrupt.
USB Host Controller
The OMAP5910 USB host controller communicates with USB devices at the USB low-speed (1.5M-bit/s
maximum) and full-speed (12M-bit/s maximum) data rates. The controller is USB compliant. For additional
information, see the Universal Serial Bus Specification, Revision 2.0 and the OpenHCI – Open Host Controller
Interface Specification for USB, Release 1.0a, hereafter called the OHCI Specification for USB.
The OMAP5910 USB host controller implements the register set and makes use of the memory data structures
which are defined in the OHCI Specification for USB. These registers and data structures are the mechanism
by which a USB host controller driver software package may control the OMAP5910 USB host controller.
The USB host controller is connected to the MPU public peripheral bus for MPU access to registers. The USB
host controller gains access to the data structures in system memory via the internal Local Bus interface. The
OMAP5910 device implements a variety of signal multiplexing options that allows use of the USB host
controller with any of the three available USB interfaces on the device. One of these interfaces utilizes an
integrated USB transceiver, while the other two require external transceivers. The host controller can support
up to three downstream ports.
Camera Interface
The camera interface is an 8-bit external port which may be used to accept data from an external camera
sensor. The interface handles multiple image formats synchronized on vertical and horizontal synchronization
signals. Data transfer to the camera interface may be done synchronously or asynchronously.
The camera interface module converts the 8-bit data transfers into 32-bit words and utilizes a 128-word buffer
to facilitate efficient data transfer to memory. Data may be transferred from the camera interface buffer to
internal memory by the system DMA controller or directly by the MPU. The interface may utilize an externally
driven clock at rates up to 13 MHz or may optionally provide an output reference clock at rates of 8 MHz,
9.6 MHz, or 24 MHz when the camera interface is configured for clocking from the internal 48 MHz. When the
camera interface is configured to obtain clocking from the base oscillator frequency (12 MHz or 13 MHz), the
camera interface clock is configurable to operate at the base frequency or one half the base frequency (6 MHz
or 6.5 MHz).
Introduction
This section describes the main features of the OMAP5910 device, lists the terminal assignments, and
describes the function of each terminal. This data manual also provides a detailed description section,
electrical specifications, parameter measurement information, and mechanical data about the available
packaging.
Description
The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application
processing needs of next-generation embedded devices.
The OMAPTM platform enables OEMs and ODMs to quickly bring to market devices featuring rich user
interfaces, high processing performance, and long battery life through the maximum flexibility of a fully
integrated mixed processor solution.
The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a
TMS320C55x DSP core and a high-performance TI925T ARM core.
The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as
well as the Texas Instruments (TI) DSP/BIOSTM software kernel foundation, and is available in a 289-ball
MicroStar BGATM package.
DSP Tools Support
The 55x DSP core is supported by the industry’s leading eXpressDSPTM software environment including the
Code Composer StudioTM integrated development environment, DSP/BIOS software kernel foundation, the
TMS320TM DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio
features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange
(RTDXTM), XDS510TM emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable
real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a
preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead.
The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of
algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’
extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions
to customers.
DSP I/O Space Memory Map
The DSP I/O space is a separate address space from the data/program memory space. The I/O space is
accessed via the DSP’s port instructions. The Public and Shared peripheral registers are also accessible by
the MPU through the MPUI (MPU Interface) port. The DSP I/O space is accessed using 16-bit word
addresses. The following tables specify the DSP base addresses where each set of registers is accessed.
All accesses to these registers must utilize the appropriate access width as indicated in the tables. Accessing
registers with the incorrect access width may cause unexpected results including a TI Peripheral Bus (TIPB)
bus error and associated TIPB interrupt.
USB Host Controller
The OMAP5910 USB host controller communicates with USB devices at the USB low-speed (1.5M-bit/s
maximum) and full-speed (12M-bit/s maximum) data rates. The controller is USB compliant. For additional
information, see the Universal Serial Bus Specification, Revision 2.0 and the OpenHCI – Open Host Controller
Interface Specification for USB, Release 1.0a, hereafter called the OHCI Specification for USB.
The OMAP5910 USB host controller implements the register set and makes use of the memory data structures
which are defined in the OHCI Specification for USB. These registers and data structures are the mechanism
by which a USB host controller driver software package may control the OMAP5910 USB host controller.
The USB host controller is connected to the MPU public peripheral bus for MPU access to registers. The USB
host controller gains access to the data structures in system memory via the internal Local Bus interface. The
OMAP5910 device implements a variety of signal multiplexing options that allows use of the USB host
controller with any of the three available USB interfaces on the device. One of these interfaces utilizes an
integrated USB transceiver, while the other two require external transceivers. The host controller can support
up to three downstream ports.
Camera Interface
The camera interface is an 8-bit external port which may be used to accept data from an external camera
sensor. The interface handles multiple image formats synchronized on vertical and horizontal synchronization
signals. Data transfer to the camera interface may be done synchronously or asynchronously.
The camera interface module converts the 8-bit data transfers into 32-bit words and utilizes a 128-word buffer
to facilitate efficient data transfer to memory. Data may be transferred from the camera interface buffer to
internal memory by the system DMA controller or directly by the MPU. The interface may utilize an externally
driven clock at rates up to 13 MHz or may optionally provide an output reference clock at rates of 8 MHz,
9.6 MHz, or 24 MHz when the camera interface is configured for clocking from the internal 48 MHz. When the
camera interface is configured to obtain clocking from the base oscillator frequency (12 MHz or 13 MHz), the
camera interface clock is configurable to operate at the base frequency or one half the base frequency (6 MHz
or 6.5 MHz).