26-05-2014, 12:32 PM
8051 Instruction Set
[attachment=63662]
Introduction
A computer instruction is made up of an operation code
(op-code) followed by either zero, one or two bytes of
operands
The op-code identifies the type of operation to be performed
while the operands identify the source and destination of the
data
The operand can be:
The data value itself
A CPU register
A memory location
An I/O port
If the instruction is associated with more than one operand,
the format is always:
Instruction
Internal Data Memory
Here is the memory map of the lower data RAM area of the C8051. Addresses 0x00
through 0x1F are the banked registers R0-R7. The active bank is controlled via the bits in
the Program Status Word (PSW). From this chart we see the bit addressable memory
located from 0x20 through 0x2F which provides 128 bits of bit addressable memory. The
upper portion is used as general purpose RAM and can be accessed by any addressing mode
(direct or indirect).
Special Function Registers
As you can see from this chart the number of SFRs has grown significantly over the original
8051. The SFRs are used as the configuration registers for peripherals within the device as
well as control functions for the core. For example, the P0MDIN is a special function
register responsible for I/O pin control. The PSW is the Program Status Word and controls
register banking and arithmetic bits like carry and overflow. All SFRs are accessed via the
direct addressing mode. Indirect addressing to these memory locations access the upper
RAM portion.
In C, abbreviated SFR names are defined in the family specific header files. For example,
the F900 SFRs are in the “C8051F930_defs.h” and “compiler_defs.h” header files.
[attachment=63662]
Introduction
A computer instruction is made up of an operation code
(op-code) followed by either zero, one or two bytes of
operands
The op-code identifies the type of operation to be performed
while the operands identify the source and destination of the
data
The operand can be:
The data value itself
A CPU register
A memory location
An I/O port
If the instruction is associated with more than one operand,
the format is always:
Instruction
Internal Data Memory
Here is the memory map of the lower data RAM area of the C8051. Addresses 0x00
through 0x1F are the banked registers R0-R7. The active bank is controlled via the bits in
the Program Status Word (PSW). From this chart we see the bit addressable memory
located from 0x20 through 0x2F which provides 128 bits of bit addressable memory. The
upper portion is used as general purpose RAM and can be accessed by any addressing mode
(direct or indirect).
Special Function Registers
As you can see from this chart the number of SFRs has grown significantly over the original
8051. The SFRs are used as the configuration registers for peripherals within the device as
well as control functions for the core. For example, the P0MDIN is a special function
register responsible for I/O pin control. The PSW is the Program Status Word and controls
register banking and arithmetic bits like carry and overflow. All SFRs are accessed via the
direct addressing mode. Indirect addressing to these memory locations access the upper
RAM portion.
In C, abbreviated SFR names are defined in the family specific header files. For example,
the F900 SFRs are in the “C8051F930_defs.h” and “compiler_defs.h” header files.