13-06-2014, 04:22 PM
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
[attachment=64860]
Abstract
This paper proposes a novel test pattern generator
(TPG) for built-in self-test. Our method generates multiple singleinput
change (MSIC) vectors in a pattern, i.e., each vector applied
to a scan chain is an SIC vector. A reconfigurable Johnson
counter and a scalable SIC counter are developed to generate
a class of minimum transition sequences. The proposed TPG is
flexible to both the test-per-clock and the test-per-scan schemes.
A theory is also developed to represent and analyze the sequences
and to extract a class of MSIC sequences. Analysis results show
that the produced MSIC sequences have the favorable features
of uniform distribution and low input transition density. The
performances of the designed TPGs and the circuits under
test with 45 nm are evaluated. Simulation results with ISCAS
benchmarks demonstrate that MSIC can save test power and
impose no more than 7.5% overhead for a scan design. It also
achieves the target fault coverage without increasing the test
length.
INTRODUCTION
BUILT-IN SELF-TEST (BIST) techniques can effectively
reduce the difficulty and complexity of VLSI testing, by
introducing on-chip test hardware into the circuit-under-test
(CUT). In conventional BIST architectures, the linear feedback
shift register (LFSR) is commonly used in the test pattern
generators (TPGs) and output response analyzers. A major
drawback of these architectures is that the pseudorandom
patterns generated by the LFSR lead to significantly high
switching activities in the CUT [1], which can cause excessive
power dissipation. They can also damage the circuit and reduce
product yield and lifetime [2], [3]. In addition, the LFSR
usually needs to generate very long pseudorandom sequences
in order to achieve the target fault coverage in nanometer
technology.
Contribution and Paper Organization
This paper presents the theory and application of a class
of minimum transition sequences. The proposed method
generates SIC sequences, and converts them to low transition
sequences for each scan chain. This can decrease the
switching activity in scan cells during scan-in shifting. The
advantages of the proposed sequence can be summarized as
follows.
1) Minimum transitions: In the proposed pattern, each
generated vector applied to each scan chain is an SIC
vector, which can minimize the input transition and
reduce test power.
2) Uniqueness of patterns: The proposed sequence does not
contain any repeated patterns, and the number of distinct
patterns in a sequence can meet the requirement of the
target fault coverage for the CUT.
3) Uniform distribution of patterns: The conventional algorithms
of modifying the test vectors generated by the
LFSR use extra hardware to get more correlated test
vectors with a low number of transitions. However, they
may reduce the randomness in the patterns, which may
result in lower fault coverage and higher test time [23].
It is proved in this paper that our multiple SIC (MSIC)
sequence is nearly uniformly distributed.
PROPOSED MSIC-TPG SCHEME
This section develops a TPG scheme that can convert an
SIC vector to unique low transition vectors for multiple scan
chains. First, the SIC vector is decompressed to its multiple
codewords. Meanwhile, the generated codewords will bit-XOR
with a same seed vector in turn. Hence, a test pattern with
similar test vectors will be applied to all scan chains. The
proposed MSIC-TPG consists of an SIC generator, a seed
generator, an XOR gate network, and a clock and control block.
CONCLUSION
This paper has proposed a low-power test pattern generation
method that could be easily implemented by hardware. It also
developed a theory to express a sequence generated by linear
sequential architectures, and extracted a class of SIC sequences
named MSIC. Analysis results showed that an MSIC sequence
had the favorable features of uniform distribution, low input
transition density, and low dependency relationship between
the test length and the TPG’s initial states. Combined with
the proposed reconfigurable Johnson counter or scalable SIC
counter, the MSIC-TPG can be easily implemented, and is
flexible to test-per-clock schemes and test-per-scan schemes.
For a test-per-clock scheme, the MSIC-TPG applies SIC
sequences to the CUT with the SRAM-like grid. For a test-perscan
scheme, the MSIC-TPG converts an SIC vector to low
transition vectors for all scan chains. Experimental results and
analysis results demonstrate that the MSIC-TPG is scalable to
scan length, and has negligible impact on the test overhead.
[attachment=64860]
Abstract
This paper proposes a novel test pattern generator
(TPG) for built-in self-test. Our method generates multiple singleinput
change (MSIC) vectors in a pattern, i.e., each vector applied
to a scan chain is an SIC vector. A reconfigurable Johnson
counter and a scalable SIC counter are developed to generate
a class of minimum transition sequences. The proposed TPG is
flexible to both the test-per-clock and the test-per-scan schemes.
A theory is also developed to represent and analyze the sequences
and to extract a class of MSIC sequences. Analysis results show
that the produced MSIC sequences have the favorable features
of uniform distribution and low input transition density. The
performances of the designed TPGs and the circuits under
test with 45 nm are evaluated. Simulation results with ISCAS
benchmarks demonstrate that MSIC can save test power and
impose no more than 7.5% overhead for a scan design. It also
achieves the target fault coverage without increasing the test
length.
INTRODUCTION
BUILT-IN SELF-TEST (BIST) techniques can effectively
reduce the difficulty and complexity of VLSI testing, by
introducing on-chip test hardware into the circuit-under-test
(CUT). In conventional BIST architectures, the linear feedback
shift register (LFSR) is commonly used in the test pattern
generators (TPGs) and output response analyzers. A major
drawback of these architectures is that the pseudorandom
patterns generated by the LFSR lead to significantly high
switching activities in the CUT [1], which can cause excessive
power dissipation. They can also damage the circuit and reduce
product yield and lifetime [2], [3]. In addition, the LFSR
usually needs to generate very long pseudorandom sequences
in order to achieve the target fault coverage in nanometer
technology.
Contribution and Paper Organization
This paper presents the theory and application of a class
of minimum transition sequences. The proposed method
generates SIC sequences, and converts them to low transition
sequences for each scan chain. This can decrease the
switching activity in scan cells during scan-in shifting. The
advantages of the proposed sequence can be summarized as
follows.
1) Minimum transitions: In the proposed pattern, each
generated vector applied to each scan chain is an SIC
vector, which can minimize the input transition and
reduce test power.
2) Uniqueness of patterns: The proposed sequence does not
contain any repeated patterns, and the number of distinct
patterns in a sequence can meet the requirement of the
target fault coverage for the CUT.
3) Uniform distribution of patterns: The conventional algorithms
of modifying the test vectors generated by the
LFSR use extra hardware to get more correlated test
vectors with a low number of transitions. However, they
may reduce the randomness in the patterns, which may
result in lower fault coverage and higher test time [23].
It is proved in this paper that our multiple SIC (MSIC)
sequence is nearly uniformly distributed.
PROPOSED MSIC-TPG SCHEME
This section develops a TPG scheme that can convert an
SIC vector to unique low transition vectors for multiple scan
chains. First, the SIC vector is decompressed to its multiple
codewords. Meanwhile, the generated codewords will bit-XOR
with a same seed vector in turn. Hence, a test pattern with
similar test vectors will be applied to all scan chains. The
proposed MSIC-TPG consists of an SIC generator, a seed
generator, an XOR gate network, and a clock and control block.
CONCLUSION
This paper has proposed a low-power test pattern generation
method that could be easily implemented by hardware. It also
developed a theory to express a sequence generated by linear
sequential architectures, and extracted a class of SIC sequences
named MSIC. Analysis results showed that an MSIC sequence
had the favorable features of uniform distribution, low input
transition density, and low dependency relationship between
the test length and the TPG’s initial states. Combined with
the proposed reconfigurable Johnson counter or scalable SIC
counter, the MSIC-TPG can be easily implemented, and is
flexible to test-per-clock schemes and test-per-scan schemes.
For a test-per-clock scheme, the MSIC-TPG applies SIC
sequences to the CUT with the SRAM-like grid. For a test-perscan
scheme, the MSIC-TPG converts an SIC vector to low
transition vectors for all scan chains. Experimental results and
analysis results demonstrate that the MSIC-TPG is scalable to
scan length, and has negligible impact on the test overhead.