14-06-2014, 04:30 PM
Resume--V.RAJESH
[attachment=64907]
Career Objective:
Seeking a challenging environment that encourages continuous learning and creativity and that provides exposure to new ideas and paves way for personal and professional growth
Key Embedded Skills
Embedded Software : Keil Version(v-3.00)
VLSI Development Tool : model sim (v-6.4b)
Operating systems : Windows XP/2007
Academic Profile
Bachelor of Technology in Electronics and Communications from SSR Institute of Engg & Technology passed out in 2012 with 67.79%.
IPE from Gowthami jr College passed out in 2008 with 79.5%.
SSC from Usodaya Vidyalayam passed out in 2006 with 75.66%.
Project Summary
Mini Project
Title : DESIGN OF ON-CHIP BUS WITH OPEN CORE PROROCOL INTERFACE
Duration : July’2010– Aug’2010
Team Size : 3
Responsibilities
Requirements Analysis (Partial involvement)
Project Planning (Partial involvement)
Application Design
S/w Module Development
Description:
It defines a high performance interface between IP cores that reduces design time,design risk and manufacturing cost for soc design.Its advancing supporting features such as configurable control signaling and test harness signals,when compared to the other protocols
Debugging Tools : MODELSIM(simulation 6.4B).
Main Project
Title : DESIGN,ANALYSIS & TESTING OF 1:8 WILKINSON POWER DIVIDER AND BEAM FORMING NETWORK FOR 30MHZ INTERFEROMETER RADAR.
Duration : 2 Months(In NARL At Tirupati Dept. Of ISRO )
Team Size : 3
Role : Team Leader
Description:
The 1st phase of this project deals with the design of 8-way Wilkinson power divider/combiner by the reference of basic type Wilkinson power divider in a 30MHz interferometer Radar and then analyze the component and test it and the 2nd phase of project deals with tilting the beam formed by array phased network without changing the antennas physically
Debugging Tools : RFSIM99
Personal Details:
Name : V.Rajesh
Date of Birth : 24th Feb’1991
Father’s Name : V.Laxminarasaiah
Sex : Male
Nationality : Indian
Permanent Address : 2-3\2,mujjugudem(v),nelakondapally(m),khammam(dist)
Languages Known : English,Telugu,Hindi
Forte : Willingness to learn, Belief in Teamwork
Hobbies : Listening music, Gaming, Making Friends, Reading books
[attachment=64907]
Career Objective:
Seeking a challenging environment that encourages continuous learning and creativity and that provides exposure to new ideas and paves way for personal and professional growth
Key Embedded Skills
Embedded Software : Keil Version(v-3.00)
VLSI Development Tool : model sim (v-6.4b)
Operating systems : Windows XP/2007
Academic Profile
Bachelor of Technology in Electronics and Communications from SSR Institute of Engg & Technology passed out in 2012 with 67.79%.
IPE from Gowthami jr College passed out in 2008 with 79.5%.
SSC from Usodaya Vidyalayam passed out in 2006 with 75.66%.
Project Summary
Mini Project
Title : DESIGN OF ON-CHIP BUS WITH OPEN CORE PROROCOL INTERFACE
Duration : July’2010– Aug’2010
Team Size : 3
Responsibilities
Requirements Analysis (Partial involvement)
Project Planning (Partial involvement)
Application Design
S/w Module Development
Description:
It defines a high performance interface between IP cores that reduces design time,design risk and manufacturing cost for soc design.Its advancing supporting features such as configurable control signaling and test harness signals,when compared to the other protocols
Debugging Tools : MODELSIM(simulation 6.4B).
Main Project
Title : DESIGN,ANALYSIS & TESTING OF 1:8 WILKINSON POWER DIVIDER AND BEAM FORMING NETWORK FOR 30MHZ INTERFEROMETER RADAR.
Duration : 2 Months(In NARL At Tirupati Dept. Of ISRO )
Team Size : 3
Role : Team Leader
Description:
The 1st phase of this project deals with the design of 8-way Wilkinson power divider/combiner by the reference of basic type Wilkinson power divider in a 30MHz interferometer Radar and then analyze the component and test it and the 2nd phase of project deals with tilting the beam formed by array phased network without changing the antennas physically
Debugging Tools : RFSIM99
Personal Details:
Name : V.Rajesh
Date of Birth : 24th Feb’1991
Father’s Name : V.Laxminarasaiah
Sex : Male
Nationality : Indian
Permanent Address : 2-3\2,mujjugudem(v),nelakondapally(m),khammam(dist)
Languages Known : English,Telugu,Hindi
Forte : Willingness to learn, Belief in Teamwork
Hobbies : Listening music, Gaming, Making Friends, Reading books