17-06-2014, 10:51 AM
SYSTEM ON CHIP (SOC) FUNDAMENTALS
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INTRODUCTION
The history of semiconductor devices starts in 1930’s when Lienfed and
Heil first proposed the mosfet. However it took 30 years before this idea was
applied to functioning devices to be used in practical applications, and up to the
late 1980 this trend took a turn when MOS technology caught up and there was a
cross over between bipolar and MOS share.CMOS was finding more wide spread
use due to its low power dissipation, high packing density and simple design, such
that by 1990 CMOS covered more than 90% of total MOS scale.
In 1983 bipolar compatible process based on CMOS technology was
developed and BiCMOS technology with both the MOS and bipolar device
fabricated on the same chip was developed and studied. The objective of the
BiCMOS is to combine bipolar and CMOS so as to exploit the advantages of both
at the circuit and system levels. Since 1985, the state-of-the-art bipolar CMOS
structures have been converging. Today BiCMOS has become one of the
dominant technologies used for high speed, low power and highly functional VLSI
circuits especially when the BiCMOS process has been enhanced and integrated in
to the CMOS process without any additional steps. Because the process step
required for both CMOS and bipolar are similar, these steps cane be shared for
both of them.
SYSTEM ON CHIP (SOC) FUNDAMENTALS
The concept of system-on-chip (SOC) has evolved as the number of gates
available to a designer has increased and as CMOS technology has migrated from
a minimum feature size of several microns to close to 0.1 μm. Over the last
decade, the integration of analog circuit blocks is an increasingly common feature
of SOC development, motivated by the desire to shrink the number of chips and
passives on a PC board. This, in turn, reduces system size and cost and improves
reliability by requiring fewer components to be mounted on a PC board. Power
dissipation of the system also improves with the elimination of the chip inputoutput
(I/O) interconnect blocks. Superior matching and control of integrated
components also allows for new circuit architectures to be used that cannot be
attempted in multi-chip architectures. Driving PC board traces consume
significant power, both in overcoming the larger capacitances on the PC board and
through larger signal swings to overcome signal cross talk and noise on the PC
board. Large-scale microcomputer systems with integrated peripherals, the
complete digital processor of cellular phone, and the switching system for a wireline
data-communication system are some of the many applications of digital SOC
systems.
Examples of analog or mixed-signal SOC devices include analog
modems; broadband wired digital communication chips, such as DSL and cable
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modems; Wireless telephone chips that combine voice band codes with base band
modulation and demodulation function; and ICs that function as the complete read
channel for disc drives. The analog section of these chips includes wideband
amplifiers, filters, phase locked loops, analog-to-digital converters, digital-toanalog
converters, operational amplifiers, current references, and voltage
references. Many of these systems take advantage of the digital processors in an
SOC chip to auto-calibrate the analog section of the chip, including canceling de
offsets and reducing linearity errors within data converters. Digital processors also
allow tuning of analog blocks, such as centering filter-cutoff frequencies. Built-in
self-test functions of the analog block are also possible through the use of on-chip
digital processors.
Analog or mixed-signal SOC integration is inappropriate for designs that
will allow low production volume and low margins. In this case, the nonrecurring
engineering costs of designing the SOC chip and its mask set will far exceed the
design cost for a system with standard programmable digital parts, standard analog
and RF functional blocks, and discrete components. Noise issues from digital
electronics can also limit the practicality of forming an SOC with high-precision
analog or RF circuits. A system that requires power-supply voltages greater than
3.6 V in its analog or RF stages is also an unattractive candidate for an SOC
because additional process modifications would be required for the silicon devices
to work above the standard printed circuit board interface voltage of 3.3 V+- 10%.
Before a high-performance analog system can be integrated on a digital
chip, the analog circuit blocks must have available critical passive components,
such as resistors and capacitors. Digital blocks, in contrast, require only n-channel
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metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor
(PMOS) transistors. Added process steps may be required to achieve
characteristics for resistors and capacitors suitable for high-performance analog
circuits. These steps create linear capacitors with low levels of parasitic
capacitance coupling to other parts of the IC, such as the substrate. Though
additional process steps may be needed for the resistors, it may be possible to
alternatively use the diffusions steps, such as the N and P implants that make up
the drains and sources of the MOS devices. The shortcomings of these elements as
resistors, as can the poly silicon gate used as part of the CMOS devices. The
shortcomings of these elements as resistors, beyond their high parasitic
capacitances, are the resistors, beyond their high parasitic capacitances, are the
resistor’s high temperature and voltage coefficients and the limited control of the
absolute value of the resistor.
Even with these additional process steps, analog engineers must cope with
small capacitor sizes (50-pf maximum) and variations in the absolute value of both
the resistors and capacitors (with no tracking between the resistors and capacitors
that could stabilize the resistor-capacitor-capacitor time constraint (RC) product).
Analog designers have developed novel circuits, such as switched capacitor
circuits, to surmount these obstacles. Indeed, CMOS enable the switched-capacitor
circuit.
Beyond component consideration, circuit layout must be done carefully to
prevent digital switching noise from degrading circuit performance. For example,
power supply routing must be carefully managed in analog circuits. The quality of
computer models for active and passive components is also a thorny issue. Models
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that are sufficiently accurate to estimate the speed performance, of digital gates
are not accurate enough to predict gain or high-frequency response. Drain
conductance, for instance, is a key analog design parameter, though it does not
affect digital gate speed. Thus, heightened attention to the modeling of active,
passive, and parasitic components is needed for the circuit to perform as expected
on its first pass through the silicon manufacturer. The introduction of RF circuits
to an SOC creates numerous problems. The circuits are sensitive to noise on the
power supply and substrate, owing to the low-level signals at which they operated
and the likelihood of correlated digital noise mixing with the nonlinear RF
components giving rise undesired spurs in the RF circuit’s outputs. Moreover, RF
circuits require their own set of active and passive components. Foremost is the
need for a high-speed, low-noise bipolar transistor. CMOS devices have yet to
demonstrate that they can be used in high volume RF systems with challenging
specification such as those found in cellular phones while concurrently offering
competitive power consumption and die area. If the RF SOC is to be competitive
with a multiple-chip or discrete-components system, the bipolar devices available
in the process that are intended for use in an RF SOC application must be state-ofthe-
art.
Inductors play a critical role in RF circuits, especially in low-noise
amplifiers, mixers, filters, power amplifiers, and oscillators. The inductor enables
the tuned narrow-band inductance-capacitance (LC) circuit. These circuits not
only filter undesired signal, but also allow for the design of circuits that can
operate over a narrow band at much higher frequencies than would be possible for
a broadband design without inductors. Oscillators, with the very low-phase noise
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required by high-performance RF systems, also need LC tank circuits. For this
application, high (larger that ten) Q-factors are required. Here, inductors are used
for impedance matching, bandwidth extension through peaking of the response,
degeneration (extension of the linear range of operation at the cost of absolute
gain) without the noise penalty of resistors, and as current sources. A current
source allows for more headroom for the active devices than an active current
source or a resistor. This is pivotal for battery-powered devices or designs that
incorporate bipolar or MOS field-effect transistors (MOSFETs) with low
breakdown voltages. Inductors must be available in an IC process that is to be
used to form an RF SOC, given their role in RF circuits.
RF circuits place additional requirements on the on-chip resistors and
capacitors. Resistors must be very linear, have minimal temperature coefficients,
have better control of absolute accuracy, and demonstrate very low parasitic
coupling to the substrate. Capacitors need high Q in RF systems. Absolute values
of the capacitors may need to be much larger than those in an analog circuit when
the capacitors are used for impedance matching, bypassing, or phase-locked loop
(PLL) filter applications.
Last, a voltage-controlled capacitor (varactor) is required to make RF
voltage -controlled oscillators with low-phase noise. Varactors are paired with
inductors to form the tuned circuit for the oscillator. A dc voltage coupled onto the
varactor tunes the oscillator frequency. Varactors may be formed from reversebiased
junctions in a process. While the grading coefficient of the PN junction is
not optimal for a large variation of capacitance with applied voltage, as in a
discrete varactor, the junctions are still useable. PN junctions available in an IC
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process include the junctions of the PMOS (in the n-well process) and NMOS (in
the p-well process) drains, as well as the bipolar BE or BC junctions. MOSFETs
can also be used as varactors since their capacitance changes as the gate voltage
changes. Limitations of on-chip varactors include poor linearity across the
tuning range, limited tuning range, and low Q. These limitations can affect circuit
performance. In a PLL, for example, low varactor Q can cause high-varactor
tuning voltage and the varactor capacitance can change PLL loop dynamics over
the range of frequencies to which the PLL locks. A tight varactor tuning range and
a large variation in the absolute capacitance value of the varactor will limit the
PLL lock range.
BIPOLAR
Bipolar devices offer superior performance attributes for many analog and
RF circuits. They can be more reliably modeled than CMOS devices at RF
frequencies and exhibit less component variation that CMOS devices at RF
frequencies. The larger design margin between circuit requirements and device
fundamental operating limits permits faster design cycle time and affords a higher
success rate for first-time silicon. First-pass success is gaining importance, as the
cost of a mask set used to process a deep sub-micron wafer can exceed
US$500,000. Early success is also desirable against the backdrop of increasing
cycle times for wafer production, package preparation, and device testing.
Bipolar devices exhibit better device-to-device matching and, thus, allow
lower input offset voltages. Bipolar devices are fundamental to voltage reference
circuits, such as band gap reference. Bipolar amplifiers exhibit lower noise,
increased bandwidth, easier matching to off chip RF passive components, and
higher gain for a given layout size and power consumption level. For a given
current level, a bipolar device always has greater transconductance than a MOS
device. Emitter-coupled logic (ECL) and current-mode logic (CML) bipolar gates
operating at very high frequencies will have less power consumption than CMOSbased
logic. The balanced current-steering structure of these logic families and the
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small switching-voltage swing moderated the on-chip radiated noise in bipolar
ECL and CML.
3.2 CMOS
In many analog and mixed-signal circuit designs, CMOS devices may be
required. CMOS devices produce excellent switches with very high off resistance
and no voltage drop when on. CMOS amplifier input stages require no dc current
flow for bias. The excellent performance of CMOS switches and the ability to
build amplifiers with an infinite input resistance is fundaments to the development
of switched-capacitor circuits. These circuits are used in precision analog-todigital
converters (ADCs) and digital-to-analog converters (DACs), as well as
comparators and filters. CMOS devices biased in the triode region can be used as
voltage-controlled resistors.
3.3 BiCMOS
BiCMOS technologies possess better integration capability than bipolaronly
technologies. It is not possible to develop very-high-density digital circuits in
bipolar-only technologies, as these bipolar logic circuits consume static power.
Also of importance to SOC systems is the vast set of large macro cells, including
microprocessors, memory macros, and DSPs, that are available in most CMOS
technologies, as well as the computer-aided design (CAD) infrastructure for multimillion
gate systems, that exist in fine-line CMOS technologies. In many analogand
mixed-signal circuit block designs, the combination of MOS and bipolar
devices results in an optimal circuit design.
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BiCMOS usually can be classified in two categories: bipolar-based
BiCMOS technology (BiCMOS optimized for high-performance bipolar
transistors) and CMOS-based Bi-CMOS technology (BiCMOS optimized for
high-speed CMOS devices). The former is often used for specialized applications
where system integration may not be large, though bipolar performance must be
maximized to ensure proper system creation. CMOS-based BiCMOS technology
is designed for high-speed signal processing ICs that may span in size from small
to large chips containing a complete communications system. Bipolar-based
BiCMOS technology must provide its own digital CMOS infrastructure while
achieving adequate return-on-investment to make the manufacturing line
profitable. In contrast, CMOS-based BiCMOS technology takes advantage of the
ever-increasing wafer size and scaled-down lithography of the most modern
CMOS production line. The quality control and throughput optimization that is
fundamental to any modern high-output CMOS fabrication facility (fab) is applied
to the manufacturing process steps involving the bipolar device. In addition, the
entire CMOS infrastructure, including modeling, standard cell libraries, largescale
macro cells, and CAD tool flows developed to design CMOS application
specified ICs (ASICs), can be applied to CMOS-based BiCMOS technology is
better suited for implementing low power wired- and wireless- communication
SOC integrated circuits and meeting time-to market requirements than a BiCMOS
process that is optimized for npn performance without preserving the
characteristics of the corresponding generation of CMOS process that is optimized
for npn performance without preserving the characteristics of the corresponding
generation of CMOS technology.
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The bipolar device should not introduce more than 10-30% additional
costs relative to the standard CMOS device; this is key for high-volume use of
BiCMOS as a SOC enabler. In addition, the BiCOMOS process must be available
as soon as possible after the fine line CMOS process becomes available. If the
development time for the bipolar module lags the CMOS by too long, it is more
likely that a multiple, the BiCMOS process must be available as soon as possible
after the fine line CMOS process becomes available. If the development time for
the bipolar module lags the CMOS by too long, it is more likely that a multiplechip
solution engineered from different device technologies may be preferred to a
single SOC implementation. It is, however, a challenging task to integrate the RF
bipolar module into a signal-processing core CMOS process without disturbing
the CMOS device characteristics and/or delaying deployment of the process.
Moreover, the bipolar process should not require a wealth of additional process
equipment that increases the cost to the fab and affects cycle-time optimization for
all process technology run in the fab.
PASSIVE COMPONENTS FOR FULLY
INTEGRATED ANALOG AND RF CIRCUITS
Several passive components are required to fully integrate analog and RF
circuits in mixed-signal SOC ICs. These included analog resistors and capacitors,
inductors, and varactors. This section describes how these elements can be
realized in the aforementioned BiCMOS process.
In the process technology presented in this article, two high-density linear
capacitors are available. Each requires one additional mask level to implement.
The metal-oxide-metal (MOM) capacitor is designed for applications that require
excellent linearity with a very low voltage coefficient (less than 40 ppm/V), and
features a density of 1.0 fF/μm2. The MOM capacitor is formed by deposition of a
35-nm oxide layer between the layers of a standard Ti/TiN/AI metal stack. The
multiple metal layers of standard CMOS are required to reduce, metal migration
under an applied field. This capacitor requires the process step of oxide
deposition, a photolithographic step to define the capacitors, an oxide etch, and a
photo strip. The processed adds no thermal cycles. The matching of a metal-metal
capacitor to an adjacent capacitor depends on the accuracy of the etching of the
capacitor. In a modern deep-submicron CMOS process, etching must be very well
controlled since metal-to-metal spacing is 0.2 μm or less. Assuming careful
layout, the MOM capacitor can match to better than 0.1% level as a result of this
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careful etch control. This allows the development of data converters of 10 b or
more without calibration or trimming.
Since the capacitor is made from metal, its series resistance is reduced. In
turn, the capacitor’s effective Q is raised. The capacitor can be placed high up in a
multiple metal stack, allowing significant reduction of the parasitic capacitance to
substrate when compared to poly-poly capacitor.
For applications that require higher density, such as bypass capacitors, a
linear MOS capacitor is available with a voltage coefficient of 0.4%/V and density
of 6.0 fF/μm2. The linear MOS capacitor used the 5.0-nm gate oxide from the 3.3-
V CMOS process with an additional arsenic implant to improve linearity.
CAPACITORS
Without any modules, a CMOS process offers only the gatesemiconductor
capacitance for capacitor formation. Not only is this highly
nonlinear as the device transition from accumulation to depletion, but it also
results in a parasitic junction capacitance on silicon side of the device that makes
the capacitor incompatible for many circuits. Traditional CMOS processes
designed for analog-and mixed-signal applications have included an extra layer of
polysilicon to form a poly-poly capacitor. This capacitor is much more linear and
its parasitic capacitance from the lower poly layer to the substrate is significantly
reduced. The introduction of the capacitor in the middle of the CMOS device
processing cycle, however, is a drawback because the thermal process affects all
the implants that precede it. More vertical topography that will affect the
achievement of planarity in the latter stages of the process is also required as metal
layers are added. From the perspective of the RF designer, the high series
resistance of a poly-poly capacitor is a major disadvantage, given its low Q value.
In the BiCMOS process technology, two high-density linear capacitors
are available. Each requires one additional mask level to implement. The metaloxide-
metal (MOM) capacitor is designed for applications that require excellent
linearity with a very low voltage coefficient (less than 40 ppm/V), and features a
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density of 1.0 fF/um2 . The MOM capacitor is formed by deposition of a 35-nm
oxide layer between the layers of a standard Ti/TiN/AI metal stack. The multiple
metal layers of standard CMOS are required to reduce, metal migration under an
applied field. This capacitor requires the process step of oxide deposition, a
photolithographic step to define the capacitors, an oxide etch, and a photo strip.
The processed adds no thermal cycles. The matching of a metal-metal capacitor to
an adjacent capacitor depends on the accuracy of the etching of the capacitor. In a
modern deep-submicron CMOS process, etching must be very well controlled
since metal-to-metal spacing is 0.2 μm or less.
Since the capacitor is made from metal, its series resistance is reduced. In
turn, the capacitor’s effective Q is raised. The capacitor can be placed high up in a
multiple metal stack, allowing significant reduction of the parasitic capacitance to
substrate when compared to poly-poly capacitor.
5.3 INDUCTORS
Conflicting substrate requirements limit the integration of high-Q
inductors with high-performance CMOS devices. Inductors fabricated using
CMOS technologies based on epi/p+ substrates [Figure 8a) are severely degraded
because of eddy-current losses in the substrate, and typically maximum qualityfactor
Q reported on epi/p+ substrates is only 3. The p+ layer has a receptivity of
roughly 0.01μ-cm and plays an important role in latch-up suppression and
impurity gettering (attracting heavy metals away from the silicon surface) in
CMOS devices.
CONCLUSION
Presented an overview of a SiGe modular BiCMOS process technology.
Through the use of add-on modules compatible with the core CMOS process
technology, large-scale chips combining digital, analog, and RF technologies can
be produced. Modules are added as required by the chip under development. By
using the core process with added modules, the economies of scale associated with
large-volume CMOS production are maintained without compromising the
performance of the analog or RF circuits. By enabling higher-speed devices and
increased device density levels, these exciting advances in process technology will
decrease the number of ICs and discrete (passive) components required by
complex optical, wired and wireless communication systems. As process
technology advances, we will see SOC systems with millions of digital gates
combined with RF circuits operating in the tens of GHz. This will be made
possible through enhanced photolithographic scaling and, potentially, SOI
technology that could result in faster devices and better isolation between circuit
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blocks. The ability to easily connect to the bodies of the MOS device remains a
problem for SOI technology when the MOS devices are used in analog or RF
circuits. Perhaps of greater significance will be the development of novel device
structures and process technology innovations as catalysts for next-generation
SOC systems.
[attachment=64958]
INTRODUCTION
The history of semiconductor devices starts in 1930’s when Lienfed and
Heil first proposed the mosfet. However it took 30 years before this idea was
applied to functioning devices to be used in practical applications, and up to the
late 1980 this trend took a turn when MOS technology caught up and there was a
cross over between bipolar and MOS share.CMOS was finding more wide spread
use due to its low power dissipation, high packing density and simple design, such
that by 1990 CMOS covered more than 90% of total MOS scale.
In 1983 bipolar compatible process based on CMOS technology was
developed and BiCMOS technology with both the MOS and bipolar device
fabricated on the same chip was developed and studied. The objective of the
BiCMOS is to combine bipolar and CMOS so as to exploit the advantages of both
at the circuit and system levels. Since 1985, the state-of-the-art bipolar CMOS
structures have been converging. Today BiCMOS has become one of the
dominant technologies used for high speed, low power and highly functional VLSI
circuits especially when the BiCMOS process has been enhanced and integrated in
to the CMOS process without any additional steps. Because the process step
required for both CMOS and bipolar are similar, these steps cane be shared for
both of them.
SYSTEM ON CHIP (SOC) FUNDAMENTALS
The concept of system-on-chip (SOC) has evolved as the number of gates
available to a designer has increased and as CMOS technology has migrated from
a minimum feature size of several microns to close to 0.1 μm. Over the last
decade, the integration of analog circuit blocks is an increasingly common feature
of SOC development, motivated by the desire to shrink the number of chips and
passives on a PC board. This, in turn, reduces system size and cost and improves
reliability by requiring fewer components to be mounted on a PC board. Power
dissipation of the system also improves with the elimination of the chip inputoutput
(I/O) interconnect blocks. Superior matching and control of integrated
components also allows for new circuit architectures to be used that cannot be
attempted in multi-chip architectures. Driving PC board traces consume
significant power, both in overcoming the larger capacitances on the PC board and
through larger signal swings to overcome signal cross talk and noise on the PC
board. Large-scale microcomputer systems with integrated peripherals, the
complete digital processor of cellular phone, and the switching system for a wireline
data-communication system are some of the many applications of digital SOC
systems.
Examples of analog or mixed-signal SOC devices include analog
modems; broadband wired digital communication chips, such as DSL and cable
101seminartopics.com
modems; Wireless telephone chips that combine voice band codes with base band
modulation and demodulation function; and ICs that function as the complete read
channel for disc drives. The analog section of these chips includes wideband
amplifiers, filters, phase locked loops, analog-to-digital converters, digital-toanalog
converters, operational amplifiers, current references, and voltage
references. Many of these systems take advantage of the digital processors in an
SOC chip to auto-calibrate the analog section of the chip, including canceling de
offsets and reducing linearity errors within data converters. Digital processors also
allow tuning of analog blocks, such as centering filter-cutoff frequencies. Built-in
self-test functions of the analog block are also possible through the use of on-chip
digital processors.
Analog or mixed-signal SOC integration is inappropriate for designs that
will allow low production volume and low margins. In this case, the nonrecurring
engineering costs of designing the SOC chip and its mask set will far exceed the
design cost for a system with standard programmable digital parts, standard analog
and RF functional blocks, and discrete components. Noise issues from digital
electronics can also limit the practicality of forming an SOC with high-precision
analog or RF circuits. A system that requires power-supply voltages greater than
3.6 V in its analog or RF stages is also an unattractive candidate for an SOC
because additional process modifications would be required for the silicon devices
to work above the standard printed circuit board interface voltage of 3.3 V+- 10%.
Before a high-performance analog system can be integrated on a digital
chip, the analog circuit blocks must have available critical passive components,
such as resistors and capacitors. Digital blocks, in contrast, require only n-channel
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metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor
(PMOS) transistors. Added process steps may be required to achieve
characteristics for resistors and capacitors suitable for high-performance analog
circuits. These steps create linear capacitors with low levels of parasitic
capacitance coupling to other parts of the IC, such as the substrate. Though
additional process steps may be needed for the resistors, it may be possible to
alternatively use the diffusions steps, such as the N and P implants that make up
the drains and sources of the MOS devices. The shortcomings of these elements as
resistors, as can the poly silicon gate used as part of the CMOS devices. The
shortcomings of these elements as resistors, beyond their high parasitic
capacitances, are the resistors, beyond their high parasitic capacitances, are the
resistor’s high temperature and voltage coefficients and the limited control of the
absolute value of the resistor.
Even with these additional process steps, analog engineers must cope with
small capacitor sizes (50-pf maximum) and variations in the absolute value of both
the resistors and capacitors (with no tracking between the resistors and capacitors
that could stabilize the resistor-capacitor-capacitor time constraint (RC) product).
Analog designers have developed novel circuits, such as switched capacitor
circuits, to surmount these obstacles. Indeed, CMOS enable the switched-capacitor
circuit.
Beyond component consideration, circuit layout must be done carefully to
prevent digital switching noise from degrading circuit performance. For example,
power supply routing must be carefully managed in analog circuits. The quality of
computer models for active and passive components is also a thorny issue. Models
101seminartopics.com
that are sufficiently accurate to estimate the speed performance, of digital gates
are not accurate enough to predict gain or high-frequency response. Drain
conductance, for instance, is a key analog design parameter, though it does not
affect digital gate speed. Thus, heightened attention to the modeling of active,
passive, and parasitic components is needed for the circuit to perform as expected
on its first pass through the silicon manufacturer. The introduction of RF circuits
to an SOC creates numerous problems. The circuits are sensitive to noise on the
power supply and substrate, owing to the low-level signals at which they operated
and the likelihood of correlated digital noise mixing with the nonlinear RF
components giving rise undesired spurs in the RF circuit’s outputs. Moreover, RF
circuits require their own set of active and passive components. Foremost is the
need for a high-speed, low-noise bipolar transistor. CMOS devices have yet to
demonstrate that they can be used in high volume RF systems with challenging
specification such as those found in cellular phones while concurrently offering
competitive power consumption and die area. If the RF SOC is to be competitive
with a multiple-chip or discrete-components system, the bipolar devices available
in the process that are intended for use in an RF SOC application must be state-ofthe-
art.
Inductors play a critical role in RF circuits, especially in low-noise
amplifiers, mixers, filters, power amplifiers, and oscillators. The inductor enables
the tuned narrow-band inductance-capacitance (LC) circuit. These circuits not
only filter undesired signal, but also allow for the design of circuits that can
operate over a narrow band at much higher frequencies than would be possible for
a broadband design without inductors. Oscillators, with the very low-phase noise
101seminartopics.com
required by high-performance RF systems, also need LC tank circuits. For this
application, high (larger that ten) Q-factors are required. Here, inductors are used
for impedance matching, bandwidth extension through peaking of the response,
degeneration (extension of the linear range of operation at the cost of absolute
gain) without the noise penalty of resistors, and as current sources. A current
source allows for more headroom for the active devices than an active current
source or a resistor. This is pivotal for battery-powered devices or designs that
incorporate bipolar or MOS field-effect transistors (MOSFETs) with low
breakdown voltages. Inductors must be available in an IC process that is to be
used to form an RF SOC, given their role in RF circuits.
RF circuits place additional requirements on the on-chip resistors and
capacitors. Resistors must be very linear, have minimal temperature coefficients,
have better control of absolute accuracy, and demonstrate very low parasitic
coupling to the substrate. Capacitors need high Q in RF systems. Absolute values
of the capacitors may need to be much larger than those in an analog circuit when
the capacitors are used for impedance matching, bypassing, or phase-locked loop
(PLL) filter applications.
Last, a voltage-controlled capacitor (varactor) is required to make RF
voltage -controlled oscillators with low-phase noise. Varactors are paired with
inductors to form the tuned circuit for the oscillator. A dc voltage coupled onto the
varactor tunes the oscillator frequency. Varactors may be formed from reversebiased
junctions in a process. While the grading coefficient of the PN junction is
not optimal for a large variation of capacitance with applied voltage, as in a
discrete varactor, the junctions are still useable. PN junctions available in an IC
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process include the junctions of the PMOS (in the n-well process) and NMOS (in
the p-well process) drains, as well as the bipolar BE or BC junctions. MOSFETs
can also be used as varactors since their capacitance changes as the gate voltage
changes. Limitations of on-chip varactors include poor linearity across the
tuning range, limited tuning range, and low Q. These limitations can affect circuit
performance. In a PLL, for example, low varactor Q can cause high-varactor
tuning voltage and the varactor capacitance can change PLL loop dynamics over
the range of frequencies to which the PLL locks. A tight varactor tuning range and
a large variation in the absolute capacitance value of the varactor will limit the
PLL lock range.
BIPOLAR
Bipolar devices offer superior performance attributes for many analog and
RF circuits. They can be more reliably modeled than CMOS devices at RF
frequencies and exhibit less component variation that CMOS devices at RF
frequencies. The larger design margin between circuit requirements and device
fundamental operating limits permits faster design cycle time and affords a higher
success rate for first-time silicon. First-pass success is gaining importance, as the
cost of a mask set used to process a deep sub-micron wafer can exceed
US$500,000. Early success is also desirable against the backdrop of increasing
cycle times for wafer production, package preparation, and device testing.
Bipolar devices exhibit better device-to-device matching and, thus, allow
lower input offset voltages. Bipolar devices are fundamental to voltage reference
circuits, such as band gap reference. Bipolar amplifiers exhibit lower noise,
increased bandwidth, easier matching to off chip RF passive components, and
higher gain for a given layout size and power consumption level. For a given
current level, a bipolar device always has greater transconductance than a MOS
device. Emitter-coupled logic (ECL) and current-mode logic (CML) bipolar gates
operating at very high frequencies will have less power consumption than CMOSbased
logic. The balanced current-steering structure of these logic families and the
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small switching-voltage swing moderated the on-chip radiated noise in bipolar
ECL and CML.
3.2 CMOS
In many analog and mixed-signal circuit designs, CMOS devices may be
required. CMOS devices produce excellent switches with very high off resistance
and no voltage drop when on. CMOS amplifier input stages require no dc current
flow for bias. The excellent performance of CMOS switches and the ability to
build amplifiers with an infinite input resistance is fundaments to the development
of switched-capacitor circuits. These circuits are used in precision analog-todigital
converters (ADCs) and digital-to-analog converters (DACs), as well as
comparators and filters. CMOS devices biased in the triode region can be used as
voltage-controlled resistors.
3.3 BiCMOS
BiCMOS technologies possess better integration capability than bipolaronly
technologies. It is not possible to develop very-high-density digital circuits in
bipolar-only technologies, as these bipolar logic circuits consume static power.
Also of importance to SOC systems is the vast set of large macro cells, including
microprocessors, memory macros, and DSPs, that are available in most CMOS
technologies, as well as the computer-aided design (CAD) infrastructure for multimillion
gate systems, that exist in fine-line CMOS technologies. In many analogand
mixed-signal circuit block designs, the combination of MOS and bipolar
devices results in an optimal circuit design.
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BiCMOS usually can be classified in two categories: bipolar-based
BiCMOS technology (BiCMOS optimized for high-performance bipolar
transistors) and CMOS-based Bi-CMOS technology (BiCMOS optimized for
high-speed CMOS devices). The former is often used for specialized applications
where system integration may not be large, though bipolar performance must be
maximized to ensure proper system creation. CMOS-based BiCMOS technology
is designed for high-speed signal processing ICs that may span in size from small
to large chips containing a complete communications system. Bipolar-based
BiCMOS technology must provide its own digital CMOS infrastructure while
achieving adequate return-on-investment to make the manufacturing line
profitable. In contrast, CMOS-based BiCMOS technology takes advantage of the
ever-increasing wafer size and scaled-down lithography of the most modern
CMOS production line. The quality control and throughput optimization that is
fundamental to any modern high-output CMOS fabrication facility (fab) is applied
to the manufacturing process steps involving the bipolar device. In addition, the
entire CMOS infrastructure, including modeling, standard cell libraries, largescale
macro cells, and CAD tool flows developed to design CMOS application
specified ICs (ASICs), can be applied to CMOS-based BiCMOS technology is
better suited for implementing low power wired- and wireless- communication
SOC integrated circuits and meeting time-to market requirements than a BiCMOS
process that is optimized for npn performance without preserving the
characteristics of the corresponding generation of CMOS process that is optimized
for npn performance without preserving the characteristics of the corresponding
generation of CMOS technology.
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The bipolar device should not introduce more than 10-30% additional
costs relative to the standard CMOS device; this is key for high-volume use of
BiCMOS as a SOC enabler. In addition, the BiCOMOS process must be available
as soon as possible after the fine line CMOS process becomes available. If the
development time for the bipolar module lags the CMOS by too long, it is more
likely that a multiple, the BiCMOS process must be available as soon as possible
after the fine line CMOS process becomes available. If the development time for
the bipolar module lags the CMOS by too long, it is more likely that a multiplechip
solution engineered from different device technologies may be preferred to a
single SOC implementation. It is, however, a challenging task to integrate the RF
bipolar module into a signal-processing core CMOS process without disturbing
the CMOS device characteristics and/or delaying deployment of the process.
Moreover, the bipolar process should not require a wealth of additional process
equipment that increases the cost to the fab and affects cycle-time optimization for
all process technology run in the fab.
PASSIVE COMPONENTS FOR FULLY
INTEGRATED ANALOG AND RF CIRCUITS
Several passive components are required to fully integrate analog and RF
circuits in mixed-signal SOC ICs. These included analog resistors and capacitors,
inductors, and varactors. This section describes how these elements can be
realized in the aforementioned BiCMOS process.
In the process technology presented in this article, two high-density linear
capacitors are available. Each requires one additional mask level to implement.
The metal-oxide-metal (MOM) capacitor is designed for applications that require
excellent linearity with a very low voltage coefficient (less than 40 ppm/V), and
features a density of 1.0 fF/μm2. The MOM capacitor is formed by deposition of a
35-nm oxide layer between the layers of a standard Ti/TiN/AI metal stack. The
multiple metal layers of standard CMOS are required to reduce, metal migration
under an applied field. This capacitor requires the process step of oxide
deposition, a photolithographic step to define the capacitors, an oxide etch, and a
photo strip. The processed adds no thermal cycles. The matching of a metal-metal
capacitor to an adjacent capacitor depends on the accuracy of the etching of the
capacitor. In a modern deep-submicron CMOS process, etching must be very well
controlled since metal-to-metal spacing is 0.2 μm or less. Assuming careful
layout, the MOM capacitor can match to better than 0.1% level as a result of this
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careful etch control. This allows the development of data converters of 10 b or
more without calibration or trimming.
Since the capacitor is made from metal, its series resistance is reduced. In
turn, the capacitor’s effective Q is raised. The capacitor can be placed high up in a
multiple metal stack, allowing significant reduction of the parasitic capacitance to
substrate when compared to poly-poly capacitor.
For applications that require higher density, such as bypass capacitors, a
linear MOS capacitor is available with a voltage coefficient of 0.4%/V and density
of 6.0 fF/μm2. The linear MOS capacitor used the 5.0-nm gate oxide from the 3.3-
V CMOS process with an additional arsenic implant to improve linearity.
CAPACITORS
Without any modules, a CMOS process offers only the gatesemiconductor
capacitance for capacitor formation. Not only is this highly
nonlinear as the device transition from accumulation to depletion, but it also
results in a parasitic junction capacitance on silicon side of the device that makes
the capacitor incompatible for many circuits. Traditional CMOS processes
designed for analog-and mixed-signal applications have included an extra layer of
polysilicon to form a poly-poly capacitor. This capacitor is much more linear and
its parasitic capacitance from the lower poly layer to the substrate is significantly
reduced. The introduction of the capacitor in the middle of the CMOS device
processing cycle, however, is a drawback because the thermal process affects all
the implants that precede it. More vertical topography that will affect the
achievement of planarity in the latter stages of the process is also required as metal
layers are added. From the perspective of the RF designer, the high series
resistance of a poly-poly capacitor is a major disadvantage, given its low Q value.
In the BiCMOS process technology, two high-density linear capacitors
are available. Each requires one additional mask level to implement. The metaloxide-
metal (MOM) capacitor is designed for applications that require excellent
linearity with a very low voltage coefficient (less than 40 ppm/V), and features a
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density of 1.0 fF/um2 . The MOM capacitor is formed by deposition of a 35-nm
oxide layer between the layers of a standard Ti/TiN/AI metal stack. The multiple
metal layers of standard CMOS are required to reduce, metal migration under an
applied field. This capacitor requires the process step of oxide deposition, a
photolithographic step to define the capacitors, an oxide etch, and a photo strip.
The processed adds no thermal cycles. The matching of a metal-metal capacitor to
an adjacent capacitor depends on the accuracy of the etching of the capacitor. In a
modern deep-submicron CMOS process, etching must be very well controlled
since metal-to-metal spacing is 0.2 μm or less.
Since the capacitor is made from metal, its series resistance is reduced. In
turn, the capacitor’s effective Q is raised. The capacitor can be placed high up in a
multiple metal stack, allowing significant reduction of the parasitic capacitance to
substrate when compared to poly-poly capacitor.
5.3 INDUCTORS
Conflicting substrate requirements limit the integration of high-Q
inductors with high-performance CMOS devices. Inductors fabricated using
CMOS technologies based on epi/p+ substrates [Figure 8a) are severely degraded
because of eddy-current losses in the substrate, and typically maximum qualityfactor
Q reported on epi/p+ substrates is only 3. The p+ layer has a receptivity of
roughly 0.01μ-cm and plays an important role in latch-up suppression and
impurity gettering (attracting heavy metals away from the silicon surface) in
CMOS devices.
CONCLUSION
Presented an overview of a SiGe modular BiCMOS process technology.
Through the use of add-on modules compatible with the core CMOS process
technology, large-scale chips combining digital, analog, and RF technologies can
be produced. Modules are added as required by the chip under development. By
using the core process with added modules, the economies of scale associated with
large-volume CMOS production are maintained without compromising the
performance of the analog or RF circuits. By enabling higher-speed devices and
increased device density levels, these exciting advances in process technology will
decrease the number of ICs and discrete (passive) components required by
complex optical, wired and wireless communication systems. As process
technology advances, we will see SOC systems with millions of digital gates
combined with RF circuits operating in the tens of GHz. This will be made
possible through enhanced photolithographic scaling and, potentially, SOI
technology that could result in faster devices and better isolation between circuit
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blocks. The ability to easily connect to the bodies of the MOS device remains a
problem for SOI technology when the MOS devices are used in analog or RF
circuits. Perhaps of greater significance will be the development of novel device
structures and process technology innovations as catalysts for next-generation
SOC systems.