17-06-2014, 02:42 PM
Introduction to Sigma Delta Converters
[attachment=64973]
How to reduce analog part
Use Sigma-Delta Conversion
Front-end simple active RC Filter
SC/Gm-C Sigma- Delta converter working at high sampling frequency
Digital Decimation Filter using DSP
Scalable with digital technology
Only few OTAs or opamps, one comparator needed, MOS switches needed
What is sigma-delta conversion
Similar to Delta Modulation but can code dc (i.e.Slowly varying signals)
Generates One bit output sequence
Output word is obtained from this sequence by finding the average using a decimator.
Also called “Pulse density modulation”
Also called “over-sampled A/D conversion”
High resolution up to 19 bits
Uses Oversampling and Noise shaping
Trades off accuracy in amplitude with accuracy in time
Advantages
Analog part small area
Over sampling ratio typically 8 to 256.
Megahertz range up to 16 bits
Band-pass Sigma –delta solutions are also available
Decimation filter
Occupies large area and consumes power.
Linear Phase FIR filter can be used.
Comb filters preferred since the input data is one bit wide only.
Can Reduce sampling rate to four times the Nyquist rate.
Lth order Noise shaping function, L+1th order decimator is required
ARCHITECTURES
Single stage Multiloop feedback
Multistage Noise Shaping (MASH)
Cascade Designs
Leslie-Singh Architecture
Single Loop Designs
No non linearity of DAC problems: only two levels one and zero.
Quantization noise power is very high and hence Need large over-sampling ratio
Single loop Sigma-delta modulators, gain progressively increases and overloads the comparator.
Delay also. Input change is felt after five stages.
High coefficient spread (large area)
Single Loop Designs
High coefficient sensitivity
Poor stability
All known digital filter structures cascade, direct form, Leap frog can be used.
Single loop Sigma delta modulators reduce integrator gin to achieve stability.
MASH
Only last stage noise ideally remains.
Noise, distortion performance and Power dissipation dependent largely on the first stage leakage.
Digital Noise cancellation circuits.
Output is a word not a bit as in the case of Single stage 1 bit A/D based design.
Complicates digital filters following the Analog blocks.
Linear single bit Quantizer in the first stage
MASH needs to have low leakage, high opamp gain 90dB low voltage applications not easily realizable.
Why Multi-bit Sigma delta converters
SNR can be improved by using multi-bit without clocking fast, Candy’s formula
Problem of mismatch of resistors/capacitors occurs
Nonlinearity of DAC is troublesome
Number of bits increases exponentially the complexity (number of capacitors/resistors)
Typically restricted to 4 or 5 bits.
Can be used as single stage Multibit or one stage of MASH
SC solution
SC preferred because of accurate control of integrator gains.
Fully Differential design increases signal swing by two and dynamic range by 6dB.
Common mode signals such as supply lines, substrate are rejected
Charges injected by switches are cancelled.
Switch Non-idealities
Fully-differential circuits recommended
Duplicated hardware; more area
Noise of switch due to ON resistance
kT/C noise, large capacitors need to be used for low noise, noise independent of Switch ON resistance Ron
Charging and discharging time dependent on
SC Sigma delta modulators OA of large bandwidth at least five times the sampling frequency and high gain are required.
COMPARATORS
Similar to OPAMPS but need logic level outputs
Input referred offset of MOS Opamps/comparators is quite high.
Offset compensation mandatory.
10 bit ADC with 1V signal, accuracy of a comparator is 1mV. Thus, residual offset has to be much smaller than 1mV
COMPARATORS
Similar to OPAMPS but need logic level outputs
Input referred offset of MOS Opamps/comparators is quite high.
Offset compensation mandatory.
10 bit ADC with 1V signal, accuracy of a comparator is 1mV. Thus, residual offset has to be much smaller than 1mV
Flash Architectures for Multibit Sigma delta converters
Quite fast
Number of comparators needed exponentially increases with bit length.
Resistor ladders needed.
Usually 4 to 5 bit Flash A/D used to reduce area.
Flash D/A converter Imperfections
Integral non-linearity
Differential non-linearity
Ac bowing due to input bias current drawn by comparators.
Comparator kickback noise during transit from latching to tracking
CT Sigma Delta Modulators
Help to increase the clock frequency
Consume less power
OSR needs to be reduced for high bandwidth applications.
No settling behavior problems.
Relaxed sampling networks
More sensitive to clock jitter
ADC jitter not much trouble
But DAC jitter troublesome. Since it is not noise shaped
Non-zero excess loop delay
Sigma delta DAC
More tolerant to component mismatch and circuit non-idealities
More digital
Keeping circuit noise low, and meeting linearity are the challenges
Power Dissipation
Settling performance of the Opamp decides gm.
Power dissipation is dependent on bias current which is decided by Gm
General Guidelines
Stability (Overload)
Long strings of ones or zeroes are detected and reset is given to integrators to improve stability.
Stabilization techniques needed e.g. clamping of integrator outputs.
Extensive simulation needed e.g Matlab Sigma Delta Tool Box R.Schrier
Rules of Thumb
Maximum of Magnitude of H(z) shall be <1.5 (Lee’s rule)
More relaxed designs available now: Magnitude of H(z) up to 6.
Idle tones in band
Conclusion
More than 400 papers
IEEE press books
Simulation tools
Months of simulation may be needed to weed out problems.
Several solutions
Applications emerging for 802.11, Blue Tooth, CDMA/GSM/3G handsets
[attachment=64973]
How to reduce analog part
Use Sigma-Delta Conversion
Front-end simple active RC Filter
SC/Gm-C Sigma- Delta converter working at high sampling frequency
Digital Decimation Filter using DSP
Scalable with digital technology
Only few OTAs or opamps, one comparator needed, MOS switches needed
What is sigma-delta conversion
Similar to Delta Modulation but can code dc (i.e.Slowly varying signals)
Generates One bit output sequence
Output word is obtained from this sequence by finding the average using a decimator.
Also called “Pulse density modulation”
Also called “over-sampled A/D conversion”
High resolution up to 19 bits
Uses Oversampling and Noise shaping
Trades off accuracy in amplitude with accuracy in time
Advantages
Analog part small area
Over sampling ratio typically 8 to 256.
Megahertz range up to 16 bits
Band-pass Sigma –delta solutions are also available
Decimation filter
Occupies large area and consumes power.
Linear Phase FIR filter can be used.
Comb filters preferred since the input data is one bit wide only.
Can Reduce sampling rate to four times the Nyquist rate.
Lth order Noise shaping function, L+1th order decimator is required
ARCHITECTURES
Single stage Multiloop feedback
Multistage Noise Shaping (MASH)
Cascade Designs
Leslie-Singh Architecture
Single Loop Designs
No non linearity of DAC problems: only two levels one and zero.
Quantization noise power is very high and hence Need large over-sampling ratio
Single loop Sigma-delta modulators, gain progressively increases and overloads the comparator.
Delay also. Input change is felt after five stages.
High coefficient spread (large area)
Single Loop Designs
High coefficient sensitivity
Poor stability
All known digital filter structures cascade, direct form, Leap frog can be used.
Single loop Sigma delta modulators reduce integrator gin to achieve stability.
MASH
Only last stage noise ideally remains.
Noise, distortion performance and Power dissipation dependent largely on the first stage leakage.
Digital Noise cancellation circuits.
Output is a word not a bit as in the case of Single stage 1 bit A/D based design.
Complicates digital filters following the Analog blocks.
Linear single bit Quantizer in the first stage
MASH needs to have low leakage, high opamp gain 90dB low voltage applications not easily realizable.
Why Multi-bit Sigma delta converters
SNR can be improved by using multi-bit without clocking fast, Candy’s formula
Problem of mismatch of resistors/capacitors occurs
Nonlinearity of DAC is troublesome
Number of bits increases exponentially the complexity (number of capacitors/resistors)
Typically restricted to 4 or 5 bits.
Can be used as single stage Multibit or one stage of MASH
SC solution
SC preferred because of accurate control of integrator gains.
Fully Differential design increases signal swing by two and dynamic range by 6dB.
Common mode signals such as supply lines, substrate are rejected
Charges injected by switches are cancelled.
Switch Non-idealities
Fully-differential circuits recommended
Duplicated hardware; more area
Noise of switch due to ON resistance
kT/C noise, large capacitors need to be used for low noise, noise independent of Switch ON resistance Ron
Charging and discharging time dependent on
SC Sigma delta modulators OA of large bandwidth at least five times the sampling frequency and high gain are required.
COMPARATORS
Similar to OPAMPS but need logic level outputs
Input referred offset of MOS Opamps/comparators is quite high.
Offset compensation mandatory.
10 bit ADC with 1V signal, accuracy of a comparator is 1mV. Thus, residual offset has to be much smaller than 1mV
COMPARATORS
Similar to OPAMPS but need logic level outputs
Input referred offset of MOS Opamps/comparators is quite high.
Offset compensation mandatory.
10 bit ADC with 1V signal, accuracy of a comparator is 1mV. Thus, residual offset has to be much smaller than 1mV
Flash Architectures for Multibit Sigma delta converters
Quite fast
Number of comparators needed exponentially increases with bit length.
Resistor ladders needed.
Usually 4 to 5 bit Flash A/D used to reduce area.
Flash D/A converter Imperfections
Integral non-linearity
Differential non-linearity
Ac bowing due to input bias current drawn by comparators.
Comparator kickback noise during transit from latching to tracking
CT Sigma Delta Modulators
Help to increase the clock frequency
Consume less power
OSR needs to be reduced for high bandwidth applications.
No settling behavior problems.
Relaxed sampling networks
More sensitive to clock jitter
ADC jitter not much trouble
But DAC jitter troublesome. Since it is not noise shaped
Non-zero excess loop delay
Sigma delta DAC
More tolerant to component mismatch and circuit non-idealities
More digital
Keeping circuit noise low, and meeting linearity are the challenges
Power Dissipation
Settling performance of the Opamp decides gm.
Power dissipation is dependent on bias current which is decided by Gm
General Guidelines
Stability (Overload)
Long strings of ones or zeroes are detected and reset is given to integrators to improve stability.
Stabilization techniques needed e.g. clamping of integrator outputs.
Extensive simulation needed e.g Matlab Sigma Delta Tool Box R.Schrier
Rules of Thumb
Maximum of Magnitude of H(z) shall be <1.5 (Lee’s rule)
More relaxed designs available now: Magnitude of H(z) up to 6.
Idle tones in band
Conclusion
More than 400 papers
IEEE press books
Simulation tools
Months of simulation may be needed to weed out problems.
Several solutions
Applications emerging for 802.11, Blue Tooth, CDMA/GSM/3G handsets