08-07-2014, 03:17 PM
ADAPTIVE NOISE CANCELLATION FILTER USING LMS ALGORITHM ON AN FPGA FOR MILITARY APPLICATIONS
[attachment=65759]
Abstract
Adaptive filters have gained popularity over the years due to their ability to adapt themselves to different environments without
substantial intervention by the user. This paper implements an adaptive noise cancellation filter on a Field Programmable Gate Array
(FPGA). The filter is designed using the Least Mean Square (LMS) algorithm due to its computational simplicity, robust behavior when
implemented in finite-precision hardware and well understood convergence behavior. To check the correctness and response of the adaptive
noise cancellation filter, the LMS algorithm is simulated using the Matlab/Simulink tool. The Simulink model is used as a reference to
implement the algorithm using the Xilinx Tool Box. To implement the adaptive filter on hardware, the System Generator (SysGen) tool in
the Xilinx block set is used to generate the bit file which is downloaded onto the FPGA through hardware co-simulation. The analysis shows
that the FPGA’s response is almost identical to that of the simulated responses. Hence, hardware implementation of the adaptive filter using
an FPGA is efficient and reliable. This paper presents the adaptive noise cancellation filter using LMS algorithm on an FPGA board
suitable for noise cancellation in Pilot helmets for Military Missions.
Introduction
In most of the noise cancellation applications, the characteristics of
the signal changes very fast and hence requires the utilization of
adaptive algorithms, which converge rapidly [1]. Hence LMS algorithm
has been used for many adaptive filter applications including
noise cancellation, echo cancellation etc. because of its simplicity
in computation and implementation [2]. An adaptive filter is a computational
device that attempts to model the relationship between
two signals in real time in an iterative manner. They are often realized
either as a set of program instructions running on an arithmetical
processing device such as a microprocessor or a digital signal
processor, or as a set of logic operations implemented in a Field-
Programmable Gate Array (FPGA) or in a VLSI integrated circuit.
Adaptive filters are self learning filters. As the signal into the adaptive
filter continues, the filter coefficients adjust themselves to
achieve the desired result, like identifying an unknown filter or cancelling
noise in the input signal.
The [Fig-1] shows the block diagram of the adaptive filter in which
an input signal x(n) is fed into the adaptive filter, that computes an
output signal y(n). The output signal is compared to a desired signal
d(n). The difference between them constitutes the error signal,
e(n). This signal is fed into a procedure which alters or adapts the
parameters of the filter in a well-defined manner.
Hardware Co-Simulation
The SysGen for DSP™ is the industry’s leading high-level tool for
designing high-performance DSP systems using FPGAs. System
Generator for DSP is part of both the DSP and System Editions of
ISE® Design Suite.
The engineers with little FPGA design experience can quickly create
production quality FPGA implementations of DSP algorithms
using System Generator for DSP. DSP modeling, Bit and cycle
accurate floating and fixed-point implementation, Automatic code
generation of VHDL or Verilog from Simulink, Hardware cosimulation,
Xilinx Power Analyzer (XPA) Integration and Hardware /
software co-design of embedded systems are the key features of
Xilinx SysGen.
Hardware Specification
The specific functions such as device-to-device interfacing, signal
processing, data communication, timing and control operations,
data display and other functions performed by a system are provided
by logic devices. They are of two types namely, Fixed logic and
Programmable logic
Result and Discussion
The bit file generated using Hardware Co-Simulation feature of SysGen for execution on the target board is downloaded onto the board via JTAG interface. The FPGA response is again taken back to Simulink via JTAG, where it is displayed. The output of the adap-tive filter and the error signal simulated using Matlab/Simullink and
[attachment=65759]
Abstract
Adaptive filters have gained popularity over the years due to their ability to adapt themselves to different environments without
substantial intervention by the user. This paper implements an adaptive noise cancellation filter on a Field Programmable Gate Array
(FPGA). The filter is designed using the Least Mean Square (LMS) algorithm due to its computational simplicity, robust behavior when
implemented in finite-precision hardware and well understood convergence behavior. To check the correctness and response of the adaptive
noise cancellation filter, the LMS algorithm is simulated using the Matlab/Simulink tool. The Simulink model is used as a reference to
implement the algorithm using the Xilinx Tool Box. To implement the adaptive filter on hardware, the System Generator (SysGen) tool in
the Xilinx block set is used to generate the bit file which is downloaded onto the FPGA through hardware co-simulation. The analysis shows
that the FPGA’s response is almost identical to that of the simulated responses. Hence, hardware implementation of the adaptive filter using
an FPGA is efficient and reliable. This paper presents the adaptive noise cancellation filter using LMS algorithm on an FPGA board
suitable for noise cancellation in Pilot helmets for Military Missions.
Introduction
In most of the noise cancellation applications, the characteristics of
the signal changes very fast and hence requires the utilization of
adaptive algorithms, which converge rapidly [1]. Hence LMS algorithm
has been used for many adaptive filter applications including
noise cancellation, echo cancellation etc. because of its simplicity
in computation and implementation [2]. An adaptive filter is a computational
device that attempts to model the relationship between
two signals in real time in an iterative manner. They are often realized
either as a set of program instructions running on an arithmetical
processing device such as a microprocessor or a digital signal
processor, or as a set of logic operations implemented in a Field-
Programmable Gate Array (FPGA) or in a VLSI integrated circuit.
Adaptive filters are self learning filters. As the signal into the adaptive
filter continues, the filter coefficients adjust themselves to
achieve the desired result, like identifying an unknown filter or cancelling
noise in the input signal.
The [Fig-1] shows the block diagram of the adaptive filter in which
an input signal x(n) is fed into the adaptive filter, that computes an
output signal y(n). The output signal is compared to a desired signal
d(n). The difference between them constitutes the error signal,
e(n). This signal is fed into a procedure which alters or adapts the
parameters of the filter in a well-defined manner.
Hardware Co-Simulation
The SysGen for DSP™ is the industry’s leading high-level tool for
designing high-performance DSP systems using FPGAs. System
Generator for DSP is part of both the DSP and System Editions of
ISE® Design Suite.
The engineers with little FPGA design experience can quickly create
production quality FPGA implementations of DSP algorithms
using System Generator for DSP. DSP modeling, Bit and cycle
accurate floating and fixed-point implementation, Automatic code
generation of VHDL or Verilog from Simulink, Hardware cosimulation,
Xilinx Power Analyzer (XPA) Integration and Hardware /
software co-design of embedded systems are the key features of
Xilinx SysGen.
Hardware Specification
The specific functions such as device-to-device interfacing, signal
processing, data communication, timing and control operations,
data display and other functions performed by a system are provided
by logic devices. They are of two types namely, Fixed logic and
Programmable logic
Result and Discussion
The bit file generated using Hardware Co-Simulation feature of SysGen for execution on the target board is downloaded onto the board via JTAG interface. The FPGA response is again taken back to Simulink via JTAG, where it is displayed. The output of the adap-tive filter and the error signal simulated using Matlab/Simullink and