18-07-2014, 04:00 PM
Review Paper on Crusoe Processor
[attachment=65979]
Abstract
Mobile computing has been the buzzword for
quite a long time. Mobile computing devices such as laptop,
desktop computer etc.are very important in day to day life
and they require microprocessor. Microprocessor is the heart
of that devices. desktop computer have very different
command on processor that’s why they require lots off
transistor and because of transistor they consume more power
due to more power processor gets heated this type of
processor is called power hungry processor. A hot processor
require cooling fan and hardware become noisier bulky. this
regard must have a proper 'performance-power' balance to
ensure commercial success. Crusoe is the new microprocessor,
which has been designed especially for the mobile computing
market. In this paper The new technology, that is Crusoe
processor is fundamentally software based: the power savings
come from replacing large numbers of transistors with
software, and operating frequency is increase up to 1GHz to
1.7GHz. software part consist of Code morphing
software(CMS),Very long instruction word(VLIW).
INTRODUCTION
Several problem are face during manufacturing the
processor that are, Energy, efficiency, Compatibility,
Performance. Energy efficiency is very important in mobile
devices where focused is directed towards battery life
verses performance. Ref.[2] To solve this problem Crusoe
processor is to design very less transistor. Due to less
transistor heat dissipation is also less.Ref.[1] Transmeta's
Crusoe x86 processor is capable of running at peak
performance with low power requirements. This allows for
a dense arrangement of CPU with minimum cooling
requirements, while achieving competitive performance
per watt.
Ref.[3] High performance processors have traditionally
relied mainly on clock frequency and superscalar
instruction issue to boost performance. while superscalar
and frequency are continuous used then they have diminish
the gain and this is appear in future. SAN MATEO, Calif.
— Transmeta Corp. will formally unveil plans on (Jan. 6)
to aim its X86-compatible with Crusoe processor at the
embedded market, where its relatively small size and low
power consumption give it an edge. Against Intel Corp. for
design wins and profitability. Ref.[4]The Crusoe Smart
Embedded (SE) processors are versions of Transmeta's
existing Crusoe 5500 and 5800 microprocessors that have
undergone a 24-hour burn-in testing process that rates them
for 10 years of operation at temperatures up to
100°C.Transmeta is also guaranteeing five years of
availability and support. Ref.[4]The company's embedded
effort started when Matt Perry, who managed the Maverick
MP3 chip group at Cirrus Logic Inc., joined Transmeta as
president in April 2002. "It's been under the covers since
Matt arrived. He had more of an embedded systems
background," said Tom Lee, director for embedded
business development at
The Code Morphing Software
Ref.[6] The Code Morphing software itself write a
program specially for the Crusoe VLIW engine.CMS has
two main part; the interpreter and the translator. Interpreter
decodes and executes x86 instructions sequentially. The
translator calculates the addresses producing the native
code from the x86 codes storing it along with any related
information in a translation cache. From then on, CMS
executes the translation until reaches the end of the
translation. Figure 4 shows an abstract flowchart of how
CMS works and the steps that it follows. The translator is
the largest and most complicated piece of the puzzle made
up of modules that decode the x86 instructions, analyze
them and generate the VLIW code by optimizing the
instructions and scheduling their execution. Without
hardware support it would be virtually impossible to have
dynamic scheduling. In the x86 ISA, when an instruction
causes an exception all instructions preceding it must finish
executing before the exception is handled. Such problem
cannot be solved without hardware support; however, this
is where commit and roll back notion discussed earlier
comes in play. The shadow registers are holding a state
prior to the exception allowing rollback so the translator
could potentially reorder faulting atoms. Same notion
applies to interrupts, where the state of the registers is
restored to the state of the shadow after the interrupt is
handled
The Translator
Upon detecting critical, frequently used x86 instruction
sequences, the Code Morphing software invokes a
Translator module that direct recompiles the x86
instructions into optimized VLIW instructions, called
―Translations‖. The native translations reduce the number
of instructions executed and results in better performance.
Further efficiencies is saving the translations in memory
that is inaccessible to normal x86 code. This special
memory area is named the ―Translation Cache‖ and allows
the Code Morphing software to re-use translations and
eliminate redundancies. Upon encountering previously
translated x86 instruction sequences, the Code Morphing
software skips the translation process and executes the
cached translation directly out of the Translating cache.
The Code Morphing software matches repeated executions
with entries in the Translation Cache and the optimized
translation is executed at full speed with minimum
overhead. The initial cost of the translation is amortized
over repeated executions
Advantages of code morphing technique
Advantages of code morphing software provides to the
Crusoe processor over traditional processor .conventional
microprocessor designs approaching 40 million transistors,
managing heat and power consumption is now one of the
industry’s biggest challenges. Switching every transistor
for on-off operation require bit of energy this is avoided in
CMS, by replacing logic transistor therefore heat
generation is very less
Integrated DDR SDRAM Memory Controller
DDR SDRAM interface is the highest performance
memory interface available on the Crusoe. The DDR
SDRAM controller supports only Double Data Rate (DDR)
SDRAM and transfers data at a rate that is twice the clock
frequency of the inter-face. This feature is absent in the
model TM 3200.The DDR SDRAM controller supports up
to four banks, the equivalent of two Dual In-line Memory
Modules (DIMMs), of DDR SDRAM using a 64-bit wide
inter-face.
Integrated SDR SDRAM Memory Controller
The SDR SDRAM memory controller supports up to
four banks, equivalent to two Small Outline Dual In-line
Memory Modules (SO-DIMMS), of Single Data Rate
(SDR) SDRAM that can be configured as 64-bit or 72-bit
SO-DIMMs. These SO-DIMMs can be populated with
64M-bit, 128M-bit or 256M-bit devices. All SO-DIMMs
must use the same frequency SDRAMs, but there are no
restrictions on mixing different SODIMM configurations
into each SO-DIMM slot. The frequency setting for the
SDR SDRAM interface is initialized during the power-on
boot sequence
[attachment=65979]
Abstract
Mobile computing has been the buzzword for
quite a long time. Mobile computing devices such as laptop,
desktop computer etc.are very important in day to day life
and they require microprocessor. Microprocessor is the heart
of that devices. desktop computer have very different
command on processor that’s why they require lots off
transistor and because of transistor they consume more power
due to more power processor gets heated this type of
processor is called power hungry processor. A hot processor
require cooling fan and hardware become noisier bulky. this
regard must have a proper 'performance-power' balance to
ensure commercial success. Crusoe is the new microprocessor,
which has been designed especially for the mobile computing
market. In this paper The new technology, that is Crusoe
processor is fundamentally software based: the power savings
come from replacing large numbers of transistors with
software, and operating frequency is increase up to 1GHz to
1.7GHz. software part consist of Code morphing
software(CMS),Very long instruction word(VLIW).
INTRODUCTION
Several problem are face during manufacturing the
processor that are, Energy, efficiency, Compatibility,
Performance. Energy efficiency is very important in mobile
devices where focused is directed towards battery life
verses performance. Ref.[2] To solve this problem Crusoe
processor is to design very less transistor. Due to less
transistor heat dissipation is also less.Ref.[1] Transmeta's
Crusoe x86 processor is capable of running at peak
performance with low power requirements. This allows for
a dense arrangement of CPU with minimum cooling
requirements, while achieving competitive performance
per watt.
Ref.[3] High performance processors have traditionally
relied mainly on clock frequency and superscalar
instruction issue to boost performance. while superscalar
and frequency are continuous used then they have diminish
the gain and this is appear in future. SAN MATEO, Calif.
— Transmeta Corp. will formally unveil plans on (Jan. 6)
to aim its X86-compatible with Crusoe processor at the
embedded market, where its relatively small size and low
power consumption give it an edge. Against Intel Corp. for
design wins and profitability. Ref.[4]The Crusoe Smart
Embedded (SE) processors are versions of Transmeta's
existing Crusoe 5500 and 5800 microprocessors that have
undergone a 24-hour burn-in testing process that rates them
for 10 years of operation at temperatures up to
100°C.Transmeta is also guaranteeing five years of
availability and support. Ref.[4]The company's embedded
effort started when Matt Perry, who managed the Maverick
MP3 chip group at Cirrus Logic Inc., joined Transmeta as
president in April 2002. "It's been under the covers since
Matt arrived. He had more of an embedded systems
background," said Tom Lee, director for embedded
business development at
The Code Morphing Software
Ref.[6] The Code Morphing software itself write a
program specially for the Crusoe VLIW engine.CMS has
two main part; the interpreter and the translator. Interpreter
decodes and executes x86 instructions sequentially. The
translator calculates the addresses producing the native
code from the x86 codes storing it along with any related
information in a translation cache. From then on, CMS
executes the translation until reaches the end of the
translation. Figure 4 shows an abstract flowchart of how
CMS works and the steps that it follows. The translator is
the largest and most complicated piece of the puzzle made
up of modules that decode the x86 instructions, analyze
them and generate the VLIW code by optimizing the
instructions and scheduling their execution. Without
hardware support it would be virtually impossible to have
dynamic scheduling. In the x86 ISA, when an instruction
causes an exception all instructions preceding it must finish
executing before the exception is handled. Such problem
cannot be solved without hardware support; however, this
is where commit and roll back notion discussed earlier
comes in play. The shadow registers are holding a state
prior to the exception allowing rollback so the translator
could potentially reorder faulting atoms. Same notion
applies to interrupts, where the state of the registers is
restored to the state of the shadow after the interrupt is
handled
The Translator
Upon detecting critical, frequently used x86 instruction
sequences, the Code Morphing software invokes a
Translator module that direct recompiles the x86
instructions into optimized VLIW instructions, called
―Translations‖. The native translations reduce the number
of instructions executed and results in better performance.
Further efficiencies is saving the translations in memory
that is inaccessible to normal x86 code. This special
memory area is named the ―Translation Cache‖ and allows
the Code Morphing software to re-use translations and
eliminate redundancies. Upon encountering previously
translated x86 instruction sequences, the Code Morphing
software skips the translation process and executes the
cached translation directly out of the Translating cache.
The Code Morphing software matches repeated executions
with entries in the Translation Cache and the optimized
translation is executed at full speed with minimum
overhead. The initial cost of the translation is amortized
over repeated executions
Advantages of code morphing technique
Advantages of code morphing software provides to the
Crusoe processor over traditional processor .conventional
microprocessor designs approaching 40 million transistors,
managing heat and power consumption is now one of the
industry’s biggest challenges. Switching every transistor
for on-off operation require bit of energy this is avoided in
CMS, by replacing logic transistor therefore heat
generation is very less
Integrated DDR SDRAM Memory Controller
DDR SDRAM interface is the highest performance
memory interface available on the Crusoe. The DDR
SDRAM controller supports only Double Data Rate (DDR)
SDRAM and transfers data at a rate that is twice the clock
frequency of the inter-face. This feature is absent in the
model TM 3200.The DDR SDRAM controller supports up
to four banks, the equivalent of two Dual In-line Memory
Modules (DIMMs), of DDR SDRAM using a 64-bit wide
inter-face.
Integrated SDR SDRAM Memory Controller
The SDR SDRAM memory controller supports up to
four banks, equivalent to two Small Outline Dual In-line
Memory Modules (SO-DIMMS), of Single Data Rate
(SDR) SDRAM that can be configured as 64-bit or 72-bit
SO-DIMMs. These SO-DIMMs can be populated with
64M-bit, 128M-bit or 256M-bit devices. All SO-DIMMs
must use the same frequency SDRAMs, but there are no
restrictions on mixing different SODIMM configurations
into each SO-DIMM slot. The frequency setting for the
SDR SDRAM interface is initialized during the power-on
boot sequence