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04-08-2014, 02:09 PM
Da-Based DCT with Error-Compensated Adder Tree
[attachment=66563]
ABSTRACT
In this paper, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is
proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine
transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is
chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DCT
core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements
outlined in the previous works.
. INTRODUCTION
Discrete cosine transform (DCT) is a widely used tool in image and video compression applications [1].
Recently, the high throughput DCT designs have been adopted to fit the requirements of real-time applications.
The high-throughput shift-adder-tree (SAT) and adder-tree (AT), those unroll the number of shifting and
addition words in parallel for DA-based computation, were introduced in [3] and [4], respectively. However, a
large truncation error occurred. In order to reduce the truncation error effect, several error compensation bias
methods have been presented [5]–[7] based on statistical analysis of the relationship between partial products
and multiplier-multiplicand. However, the elements of the truncation part outlined in this work are independent
so that the previously described compensation methods cannot be applied. This brief addresses a DA-based
DCT core with an error-compensated adder-tree (ECAT).The proposed ECAT operates shifting and addition in
parallel by unrolling all the words required to be computed. Furthermore, the error-compensated circuit
alleviates the truncation error for high accuracy design.
. CONCLUSION
In this brief, a high-speed and low-error 8 × 8 2-D DCT design with ECAT is proposed to improve the
throughput rate significantly up to about 13 folds at high compression rates by operating the shifting and
addition in parallel. Furthermore, the proposed error-compensated circuit alleviates the truncation error in ECAT. In this way, the DA-precision can be chosen as 9 bits instead of 12 bits so as to meet the PSNR
requirements. Thus, the proposed DCT core has the highest hardware efficiency than those in previous works
for the same PSNR requirements. Finally, an area-efficient 2-D DCT core is implemented using a TSMC 0.18-
_m process, and the maximum throughput rate is 1 Gpels/s. In summary, the proposed architecture is suitable
for high compression rate applications in VLSI designs
[attachment=66563]
ABSTRACT
In this paper, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is
proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine
transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is
chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DCT
core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements
outlined in the previous works.
. INTRODUCTION
Discrete cosine transform (DCT) is a widely used tool in image and video compression applications [1].
Recently, the high throughput DCT designs have been adopted to fit the requirements of real-time applications.
The high-throughput shift-adder-tree (SAT) and adder-tree (AT), those unroll the number of shifting and
addition words in parallel for DA-based computation, were introduced in [3] and [4], respectively. However, a
large truncation error occurred. In order to reduce the truncation error effect, several error compensation bias
methods have been presented [5]–[7] based on statistical analysis of the relationship between partial products
and multiplier-multiplicand. However, the elements of the truncation part outlined in this work are independent
so that the previously described compensation methods cannot be applied. This brief addresses a DA-based
DCT core with an error-compensated adder-tree (ECAT).The proposed ECAT operates shifting and addition in
parallel by unrolling all the words required to be computed. Furthermore, the error-compensated circuit
alleviates the truncation error for high accuracy design.
. CONCLUSION
In this brief, a high-speed and low-error 8 × 8 2-D DCT design with ECAT is proposed to improve the
throughput rate significantly up to about 13 folds at high compression rates by operating the shifting and
addition in parallel. Furthermore, the proposed error-compensated circuit alleviates the truncation error in ECAT. In this way, the DA-precision can be chosen as 9 bits instead of 12 bits so as to meet the PSNR
requirements. Thus, the proposed DCT core has the highest hardware efficiency than those in previous works
for the same PSNR requirements. Finally, an area-efficient 2-D DCT core is implemented using a TSMC 0.18-
_m process, and the maximum throughput rate is 1 Gpels/s. In summary, the proposed architecture is suitable
for high compression rate applications in VLSI designs