seminar code
05-08-2014, 12:27 PM
Design and Implementation of low power error tolerant Adder
[attachment=66600]
Abstract
In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from the least significant bit (LSB) to the most significant bit (MSB). Also glitches in the carry propagation chain dissipate a significant proportion of dynamic power dissipation. Therefore, if the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved, Delay and Power estimation for different number of bits is estimated
INTRODUCTION
Adder is one among the fundamental components of many digital and non-digital systems and hence, their power dissipation and speed are of prime concern. In portable analog applications where power consumption is the most important parameter, one should reduce power dissipation to the possible limit. In analog computations, generation of “good enough” results is more important than totally accurate results .Hence, by adopting error tolerance concept in design and test; it is possible to generate good enough results .To deal with high speed and low power circuits for analog computations
CONVENTIONAL ADDER
Ripple-Carry Adder (RCA): The n-bit adder is built from n-one-bit full adders is known as a ripple carry adder, because of the way the carry is computed. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit “ripples” to the next full adder. Block diagram of Ripple Carry Adder is as in Fig.
Error-tolerant adder
Before detailing the ETA, the definitions of some commonly used terminologies shown in this study are given as follows:
•Overall error (OE) OE = Rc-RE, where RE, is the result obtained by the adder and Rc denotes the correct result (all the results are represented as decimal numbers)
•Accuracy (ACC): In the scenario of the error-tolerant design, the accuracy of an adder is used to indicate how “correct” the output of an adder is for a particular input. It is defined as: ACC = (1-(OE/Rc))/100%
•Its value ranges from 0-100%.
•Minimum Acceptable Accuracy (MAA): Although some errors are allowed to exist at the output of an ETA, the accuracy of an acceptable output should be “high enough” (higher than a threshold value) to meet the requirement of the whole system. Minimum acceptable accuracy is just that threshold value. The result obtained whose accuracy is higher than the minimum acceptable accuracy is called acceptable result.
•Acceptance Probability (AP): Acceptance probability is the probability that the accuracy of an adder is higher than the minimum acceptable accuracy
Design of the accurate part
Ripple carry addition is the most power saving conventional addition technique .the Ripple carry adder is built from cascading the full adders in series the full adder block diagram is as shown below fig 3
Design of the inaccurate part
The inaccurate part is the most critical section in the proposed ETA as it determines the accuracy, speed performance, and power consumption of the adder. The inaccurate part consists of two blocks: the carry free addition block and the control block. The carry-free addition block is designed using 4 modified XOR gates to generate a sum bit individually for LSBs. The function of the control block is to detect the first bit position when both input bits are “1,” and to set the control signal CTL to high at this position as well as those to its right up to LSB .The block diagram of the carry free addition block and the schematic implementation of the modified XOR gate are shown in the fig below fig.4 and it’s control logic block diagram shown in fig.5.
Conclusion
The proposed Error Tolerant Adder trades a certain amount of accuracy for significant power saving and performance improvement. Extensive comparisons with conventional Adders i.e. Ripple Carry Adder is shown in the table.2 indicate that the proposed ETA out-performed the conventional Adders Applications Power Performance.
[attachment=66600]
Abstract
In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from the least significant bit (LSB) to the most significant bit (MSB). Also glitches in the carry propagation chain dissipate a significant proportion of dynamic power dissipation. Therefore, if the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved, Delay and Power estimation for different number of bits is estimated
INTRODUCTION
Adder is one among the fundamental components of many digital and non-digital systems and hence, their power dissipation and speed are of prime concern. In portable analog applications where power consumption is the most important parameter, one should reduce power dissipation to the possible limit. In analog computations, generation of “good enough” results is more important than totally accurate results .Hence, by adopting error tolerance concept in design and test; it is possible to generate good enough results .To deal with high speed and low power circuits for analog computations
CONVENTIONAL ADDER
Ripple-Carry Adder (RCA): The n-bit adder is built from n-one-bit full adders is known as a ripple carry adder, because of the way the carry is computed. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit “ripples” to the next full adder. Block diagram of Ripple Carry Adder is as in Fig.
Error-tolerant adder
Before detailing the ETA, the definitions of some commonly used terminologies shown in this study are given as follows:
•Overall error (OE) OE = Rc-RE, where RE, is the result obtained by the adder and Rc denotes the correct result (all the results are represented as decimal numbers)
•Accuracy (ACC): In the scenario of the error-tolerant design, the accuracy of an adder is used to indicate how “correct” the output of an adder is for a particular input. It is defined as: ACC = (1-(OE/Rc))/100%
•Its value ranges from 0-100%.
•Minimum Acceptable Accuracy (MAA): Although some errors are allowed to exist at the output of an ETA, the accuracy of an acceptable output should be “high enough” (higher than a threshold value) to meet the requirement of the whole system. Minimum acceptable accuracy is just that threshold value. The result obtained whose accuracy is higher than the minimum acceptable accuracy is called acceptable result.
•Acceptance Probability (AP): Acceptance probability is the probability that the accuracy of an adder is higher than the minimum acceptable accuracy
Design of the accurate part
Ripple carry addition is the most power saving conventional addition technique .the Ripple carry adder is built from cascading the full adders in series the full adder block diagram is as shown below fig 3
Design of the inaccurate part
The inaccurate part is the most critical section in the proposed ETA as it determines the accuracy, speed performance, and power consumption of the adder. The inaccurate part consists of two blocks: the carry free addition block and the control block. The carry-free addition block is designed using 4 modified XOR gates to generate a sum bit individually for LSBs. The function of the control block is to detect the first bit position when both input bits are “1,” and to set the control signal CTL to high at this position as well as those to its right up to LSB .The block diagram of the carry free addition block and the schematic implementation of the modified XOR gate are shown in the fig below fig.4 and it’s control logic block diagram shown in fig.5.
Conclusion
The proposed Error Tolerant Adder trades a certain amount of accuracy for significant power saving and performance improvement. Extensive comparisons with conventional Adders i.e. Ripple Carry Adder is shown in the table.2 indicate that the proposed ETA out-performed the conventional Adders Applications Power Performance.