project maker
09-08-2014, 04:34 PM
DESIGN AND IMPELIMENTATION
[attachment=66827]
ABSTRACT
A new FPGA-based implementation scheme of the AES-128 (Advanced Encryption Standard, with 128-bit key) encryption algorithm is proposed in this project. For maintaining the speed of encryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that bit initial key, as well as the 128-bit output of ciphertext, is all divided into four 32-bit consecutive units respectively controlled by the clock. The synthesis verification based on CMOS process shows that this new program can significantly decrease quantity of chip pins and effectively optimize the area of chip.
Shift Rows (Shift rows Operation):
As implied by its name, the Shift rows operation processes different rows. A simple rotate with a different rotate width is performed. The second row of the 4x4 byte input data (the state) is shifted one byte position to the left in the matrix, the third row is shifted two byte positions to the left, and the fourth row is shifted three byte positions to the left. The first row is not changed.
Mix Columns (Mix columns Operation):
Opposed to the ShiftRows operation, which works on rows in the 4x4 state matrixes, the Mix columns operation processes columns. Transformation in the Cipher that takes all of the columns of the State and mixes their data (independently of one another) to produce new columns shown in figure 7.
Pipelining Technology:
In computers, a pipeline is the continuous and somewhat overlapped movement of instruction to the processor or in the arithmetic steps taken by the processor to perform an instruction. Pipelining is the use of a pipeline. Without a pipeline, a computer processor gets the first instruction from memory, performs the operation it calls for, and then goes to get the next instruction from memory, and so forth. While fetching (getting) the instruction, the arithmetic part of the processor is idle. It must wait until it gets the next instruction.
With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can be performed. The staging of instruction fetching is continuous. The result is an increase in the number of instructions that can be performed during a given time period.
Pipelining is sometimes compared to a manufacturing assembly line in which different parts of a product are being assembled at the same time although ultimately there may be some parts that have to be assembled before others are. Even if there is some sequential dependency, the overall process can take advantage of those operations that can proceed concurrently.
Computer processor pipelining is sometimes divided into an instruction pipeline and an arithmetic pipeline. The instruction pipeline represents the stages in which an instruction is moved through the processor, including its being fetched, perhaps buffered, and then executed. The arithmetic pipeline represents the parts of an arithmetic operation that can be broken down and overlapped as they are performed.
Pipelines and pipelining also apply to computer memory controllers and moving data through various memory staging places.
Computer processors can handle millions of instructions each second. Once one instruction is processed, the next one in line is processed, and so on. A pipeline allows multiple instructions to be processed at the same time. While one stage of an instruction is being processed, other instructions may be undergoing processing at a different stage. Without a pipeline, each instruction would have to wait for the previous one to finish before it could even be accessed.
To understand the benefit of a pipeline, imagine that a car manufacturing plant had to wait for each car to be fully completed before starting on the next one. That would be horribly inefficient, right? It makes much more sense to work on many cars at once, completing them one stage at a time. This is what a pipeline in a computer allows. Pipelining, as it is called, often keeps around six instructions at once in the processor at different stages of processing. Pipelines can be used for the CPU as well as for accessing memory.
Interconnect:
Multiple copies of CLB slices are arranged in a matrix on the surface of the chip. The CLBs are connected column-wise and row-wise. At the intersections of columns and rows are programmable switch matrices (PSM). This can be seen in figure 12. In this figure the output of one CLB is connected with the inputs of two other CLBs. The signal passes through three PIPs and two PSMs. While the PSMs make the FPGA versatile, they slow down the signals. Therefore FPGA implementation become considerable slower than their ASIC counterparts. Therefore FPGA designers added many other interconnect in addition to PIPs and PSMs. Some architectures implement nearest neighbor routs. There are also routes that skip some PSM. Furthermore, there are extra routes for e.g. reset lines or clock lines.
[attachment=66827]
ABSTRACT
A new FPGA-based implementation scheme of the AES-128 (Advanced Encryption Standard, with 128-bit key) encryption algorithm is proposed in this project. For maintaining the speed of encryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that bit initial key, as well as the 128-bit output of ciphertext, is all divided into four 32-bit consecutive units respectively controlled by the clock. The synthesis verification based on CMOS process shows that this new program can significantly decrease quantity of chip pins and effectively optimize the area of chip.
Shift Rows (Shift rows Operation):
As implied by its name, the Shift rows operation processes different rows. A simple rotate with a different rotate width is performed. The second row of the 4x4 byte input data (the state) is shifted one byte position to the left in the matrix, the third row is shifted two byte positions to the left, and the fourth row is shifted three byte positions to the left. The first row is not changed.
Mix Columns (Mix columns Operation):
Opposed to the ShiftRows operation, which works on rows in the 4x4 state matrixes, the Mix columns operation processes columns. Transformation in the Cipher that takes all of the columns of the State and mixes their data (independently of one another) to produce new columns shown in figure 7.
Pipelining Technology:
In computers, a pipeline is the continuous and somewhat overlapped movement of instruction to the processor or in the arithmetic steps taken by the processor to perform an instruction. Pipelining is the use of a pipeline. Without a pipeline, a computer processor gets the first instruction from memory, performs the operation it calls for, and then goes to get the next instruction from memory, and so forth. While fetching (getting) the instruction, the arithmetic part of the processor is idle. It must wait until it gets the next instruction.
With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can be performed. The staging of instruction fetching is continuous. The result is an increase in the number of instructions that can be performed during a given time period.
Pipelining is sometimes compared to a manufacturing assembly line in which different parts of a product are being assembled at the same time although ultimately there may be some parts that have to be assembled before others are. Even if there is some sequential dependency, the overall process can take advantage of those operations that can proceed concurrently.
Computer processor pipelining is sometimes divided into an instruction pipeline and an arithmetic pipeline. The instruction pipeline represents the stages in which an instruction is moved through the processor, including its being fetched, perhaps buffered, and then executed. The arithmetic pipeline represents the parts of an arithmetic operation that can be broken down and overlapped as they are performed.
Pipelines and pipelining also apply to computer memory controllers and moving data through various memory staging places.
Computer processors can handle millions of instructions each second. Once one instruction is processed, the next one in line is processed, and so on. A pipeline allows multiple instructions to be processed at the same time. While one stage of an instruction is being processed, other instructions may be undergoing processing at a different stage. Without a pipeline, each instruction would have to wait for the previous one to finish before it could even be accessed.
To understand the benefit of a pipeline, imagine that a car manufacturing plant had to wait for each car to be fully completed before starting on the next one. That would be horribly inefficient, right? It makes much more sense to work on many cars at once, completing them one stage at a time. This is what a pipeline in a computer allows. Pipelining, as it is called, often keeps around six instructions at once in the processor at different stages of processing. Pipelines can be used for the CPU as well as for accessing memory.
Interconnect:
Multiple copies of CLB slices are arranged in a matrix on the surface of the chip. The CLBs are connected column-wise and row-wise. At the intersections of columns and rows are programmable switch matrices (PSM). This can be seen in figure 12. In this figure the output of one CLB is connected with the inputs of two other CLBs. The signal passes through three PIPs and two PSMs. While the PSMs make the FPGA versatile, they slow down the signals. Therefore FPGA implementation become considerable slower than their ASIC counterparts. Therefore FPGA designers added many other interconnect in addition to PIPs and PSMs. Some architectures implement nearest neighbor routs. There are also routes that skip some PSM. Furthermore, there are extra routes for e.g. reset lines or clock lines.