12-08-2014, 10:18 AM
Hard Multiple Generator for Higher Radix Modulo
[attachment=66560]
Abstract
—High-speed modulo multipliers are essential
elements in RNS datapath. Booth recoding algorithm can be used
to improve the performance of the multiplier by reducing the
number of partial products. In radix-8 Booth encoding, the
number of partial products is reduced to one-third. However, the
inevitable carry propagation adder required to generate the hard
multiple, 3X, where X is the multiplicand, falls on the critical
path of the multiplier. This paper presents an efficient modulo
2n
−1 hard multiple generator based on the parallel-prefix
addition. The proposed hard multiple generator employs
2 ⎡ ⎤ ⎢ ⎥ log 1 n − prefix levels, making radix-8 Booth encoding a
feasible choice for high-speed modulo 2n
−1 multiplier design. The
merit of the design is corroborated by synthesis results based on
TSMC 0.18μm CMOS standard-cell library.
INTRODUCTION
Modulo 2n
−1 multiplication is used extensively in Residue
Number System (RNS) based Digital Signal Processing (DSP)
and cryptography units. High-speed modulo Modulo 2n
CONCLUSION
In radix-8 Booth encoded modulo 2n
−1 multiplier, the
generation of the hard multiple degrades the performance of the
multiplier due to the long word-length carry propagation adder.
An efficient parallel-prefix modulo 2n
−1 HMG was proposed in
this paper. The performance of the proposed HMG was
evaluated against existing modulo 2n
−1 adders both analytically
and by synthesis results. It was found that the proposed HMG
significantly reduces the area and delay complexity for any n
[attachment=66560]
Abstract
—High-speed modulo multipliers are essential
elements in RNS datapath. Booth recoding algorithm can be used
to improve the performance of the multiplier by reducing the
number of partial products. In radix-8 Booth encoding, the
number of partial products is reduced to one-third. However, the
inevitable carry propagation adder required to generate the hard
multiple, 3X, where X is the multiplicand, falls on the critical
path of the multiplier. This paper presents an efficient modulo
2n
−1 hard multiple generator based on the parallel-prefix
addition. The proposed hard multiple generator employs
2 ⎡ ⎤ ⎢ ⎥ log 1 n − prefix levels, making radix-8 Booth encoding a
feasible choice for high-speed modulo 2n
−1 multiplier design. The
merit of the design is corroborated by synthesis results based on
TSMC 0.18μm CMOS standard-cell library.
INTRODUCTION
Modulo 2n
−1 multiplication is used extensively in Residue
Number System (RNS) based Digital Signal Processing (DSP)
and cryptography units. High-speed modulo Modulo 2n
CONCLUSION
In radix-8 Booth encoded modulo 2n
−1 multiplier, the
generation of the hard multiple degrades the performance of the
multiplier due to the long word-length carry propagation adder.
An efficient parallel-prefix modulo 2n
−1 HMG was proposed in
this paper. The performance of the proposed HMG was
evaluated against existing modulo 2n
−1 adders both analytically
and by synthesis results. It was found that the proposed HMG
significantly reduces the area and delay complexity for any n