18-08-2014, 12:28 PM
Seminar Report On A Very Fast and Low Power Carry Select Adder Circuit
[attachment=66702]
Abstract
Carry Select Adder (CSA) is known to be the fastest
adder among the conventional adder structures. It is used in
many data processing units for realizing faster arithmetic
operations. In this paper, we present an innovative CSA
architecture. It employs a novel incrementer circuit in the
interim stages of the CSA. Validation of the proposed design is
done through design and implementation of 16, 32 and 64-bit
adder circuits. Comparisons with existing conventional fast
adder architectures have been made to prove its efficiency. The
performance analysis shows that the proposed architecture
achieves three fold advantages in terms of delay-area-power.
INTRODUCTION
The design of high-speed and low-power VLSI
architectures needs efficient arithmetic processing units,
which are optimized for the performance parameters, namely,
speed and power consumption. Adders are the key
components in general purpose microprocessors and digital
signal processors. They also find use in many other functions
such as subtraction, multiplication and division. As a result,
it is very pertinent that its performance augers well for their
speed performance. Furthermore, for the applications such as
the RISC processor design, where single cycle execution of
instructions is the key measure of performance of the circuits,
use of an efficient adder circuit becomes necessary, to realize
efficient system performance. Additionally, the area is an
essential factor which is to be taken into account in the
design of fast adders. Towards this end, high-speed, low
power and area efficient addition and multiplication has
always been a fundamental requirement of high-performance
processors and systems. The major speed limitation of adders
arises from the huge carry propagation delay encountered in
the conventional adder circuits, such as ripple carry adder
and carry save adder.
CONVENTIONAL ADDER CIRCUITS
Fig.1 shows the internal logic schematic of a carry select
adder constructed using the conventional 4-bit ripple carry
adder (RCA). The RCA uses multiple full adders to perform
addition operation. Each full adder inputs a carry-in, which is
the carry-out of the preceding adder. The CSA divides the
words to be added into blocks and forms two sums for each
block in parallel, one with assumed carry in (Cin) of 0 and
the other with Cin of 1. As shown in Fig. 1, the carry-out
from one stage of 4- bit RCA is used as the select signal for
the multiplexer. This selects the corresponding sum bit from
the next block of data. This speeds-up the computation
process of the adder. Thus, the carry select adder achieves
higher speed of operation at the cost of increased number of
devices used in the circuit. This in turn increases the area and
power consumed by the circuits of this type of structure
ASIC IMPLEMENTATION AND RESULT
The circuit design in this paper has been developed using
Verilog-HDL and synthesized in Synopsys Front-end Design
Vision tool using SAED 90nm generic library. Table I
exhibits the post layout simulation results of both the
conventional and proposed adder structures in terms of delay,
area and power. The area indicates the total cell area of the
design; the total power is the sum of dynamic power, internal
power, net power and leakage power. The delay is the critical
path delay of the adder circuits.
The results depicted in Fig. 4 shows that the proposed
CSA has higher speed when compared to conventional CSA
and carry save adder. The marginal improvement in speed
increases with the rise in the word size of the adders. This
shows that the design can be very well incorporated into
complex VLSI Designs and DSP applications in order to
increase the operating speed of the circuits.
Figure 5 compares the adder circuits for the area
comparisons. It shows that the area of the conventional carry
select adder is more than the carry save adder whereas the
proposed circuit occupies a lesser area when compared to its
conventional adder counterparts. The quantum of area gain
achieved in the proposed circuit increases with the increase
in the word-size of the adders.
CONCLUSION
The proposed structure proves to be a easier solution for
improving the speed of carry select adder. The conventional
CSA suffers from the disadvantage of occupying more chip
area, which has been overcome using the proposed 4-bit
incrementer unit. The proposed unit is also found to consume
less power. The proposed carry select adder can be used to
speed up the final addition in parallel multiplier circuits and
other architectures which uses adder circuits. The structure
has been synthesized with Synopsys front-end bundle using
SAED 90nm technology.
[attachment=66702]
Abstract
Carry Select Adder (CSA) is known to be the fastest
adder among the conventional adder structures. It is used in
many data processing units for realizing faster arithmetic
operations. In this paper, we present an innovative CSA
architecture. It employs a novel incrementer circuit in the
interim stages of the CSA. Validation of the proposed design is
done through design and implementation of 16, 32 and 64-bit
adder circuits. Comparisons with existing conventional fast
adder architectures have been made to prove its efficiency. The
performance analysis shows that the proposed architecture
achieves three fold advantages in terms of delay-area-power.
INTRODUCTION
The design of high-speed and low-power VLSI
architectures needs efficient arithmetic processing units,
which are optimized for the performance parameters, namely,
speed and power consumption. Adders are the key
components in general purpose microprocessors and digital
signal processors. They also find use in many other functions
such as subtraction, multiplication and division. As a result,
it is very pertinent that its performance augers well for their
speed performance. Furthermore, for the applications such as
the RISC processor design, where single cycle execution of
instructions is the key measure of performance of the circuits,
use of an efficient adder circuit becomes necessary, to realize
efficient system performance. Additionally, the area is an
essential factor which is to be taken into account in the
design of fast adders. Towards this end, high-speed, low
power and area efficient addition and multiplication has
always been a fundamental requirement of high-performance
processors and systems. The major speed limitation of adders
arises from the huge carry propagation delay encountered in
the conventional adder circuits, such as ripple carry adder
and carry save adder.
CONVENTIONAL ADDER CIRCUITS
Fig.1 shows the internal logic schematic of a carry select
adder constructed using the conventional 4-bit ripple carry
adder (RCA). The RCA uses multiple full adders to perform
addition operation. Each full adder inputs a carry-in, which is
the carry-out of the preceding adder. The CSA divides the
words to be added into blocks and forms two sums for each
block in parallel, one with assumed carry in (Cin) of 0 and
the other with Cin of 1. As shown in Fig. 1, the carry-out
from one stage of 4- bit RCA is used as the select signal for
the multiplexer. This selects the corresponding sum bit from
the next block of data. This speeds-up the computation
process of the adder. Thus, the carry select adder achieves
higher speed of operation at the cost of increased number of
devices used in the circuit. This in turn increases the area and
power consumed by the circuits of this type of structure
ASIC IMPLEMENTATION AND RESULT
The circuit design in this paper has been developed using
Verilog-HDL and synthesized in Synopsys Front-end Design
Vision tool using SAED 90nm generic library. Table I
exhibits the post layout simulation results of both the
conventional and proposed adder structures in terms of delay,
area and power. The area indicates the total cell area of the
design; the total power is the sum of dynamic power, internal
power, net power and leakage power. The delay is the critical
path delay of the adder circuits.
The results depicted in Fig. 4 shows that the proposed
CSA has higher speed when compared to conventional CSA
and carry save adder. The marginal improvement in speed
increases with the rise in the word size of the adders. This
shows that the design can be very well incorporated into
complex VLSI Designs and DSP applications in order to
increase the operating speed of the circuits.
Figure 5 compares the adder circuits for the area
comparisons. It shows that the area of the conventional carry
select adder is more than the carry save adder whereas the
proposed circuit occupies a lesser area when compared to its
conventional adder counterparts. The quantum of area gain
achieved in the proposed circuit increases with the increase
in the word-size of the adders.
CONCLUSION
The proposed structure proves to be a easier solution for
improving the speed of carry select adder. The conventional
CSA suffers from the disadvantage of occupying more chip
area, which has been overcome using the proposed 4-bit
incrementer unit. The proposed unit is also found to consume
less power. The proposed carry select adder can be used to
speed up the final addition in parallel multiplier circuits and
other architectures which uses adder circuits. The structure
has been synthesized with Synopsys front-end bundle using
SAED 90nm technology.