18-08-2014, 03:30 PM
SEMINAR REPORT ON POWER REDUCTION TECHNIQUES IN CMOS IMAGE SENSOR
[attachment=66720]
INTRODUCTION
An image sensor is a device that converts an optical image into an electronic signal. It is used mostly in digital cameras, camera modules and other imaging devices.Most currently used image sensors are charge-coupled device (CCD) and complementary metal oxide–semiconductor (CMOS) sensors. Charge-coupled devices (CCDs) have traditionally been the dominant image-sensor technology. Recent advances in the design of image sensors implemented in complementary metaloxide semiconductor (CMOS) technologies have led to their adoption in several high-volume products, such as the optical mouse, PC cameras, mobile phones, and high-end digital cameras, making them a viable alternative to CCDs. For improving the performance of CMOS image sensor Power reduction techniques are necessary
Power Reduction Methods in Cmos Image Sensor
CMOS imagers naturally provide low-power dissipation, their wide utilization in various portable battery-operated devices generates an increased demand for more aggressive power reduction. There are many ways to reduce power dissipation in CMOS image sensors. Usually, the target is achieved by continuous technology
scaling and aggressive supply voltage reduction . However, in contrast to conventional digital circuits that achieve reduced area and better performance in state-of-the-art submicron processes, CMOS image sensors are more sensitive to technology scaling, requiring a stable, well-characterized technology. In addition to reduced photo collection efficiency and increased dark current, technology scaling and supply voltage reduction significantly affect the output swing of the sensor, producing a serious impact on the signal-to-noise ratio and dynamic range of the imager
Power Reduction at the Algorithm and Architecture Levels[2][3]
Power reduction through the algorithm selection is based on minimizing the number of operations and hence the number of required hardware resources. In conventional cameras-on-a-chip there are not so many options to reduce power dissipation through the algorithm level. Usually these imagers are limited by rolling or global shutter operation requirements and are expected to provide full resolution analog/digital grayscale/color image at the required frame rate . Many low power imagers are not required to provide a full resolution image at real time.
Power dissipation reduction at the algorithm level can be done by following methods (a) operational activity of different processing blocks should be reduced, (b) only windows of interest, consisting of the required features, should be defined and activated, while cutting off the remaining pixels of the array and periphery circuitry, responsible for their operation, © image transfer for further processing should be performed only in the cases where it is essential (d) computation of the required functions based on the computation results from the previous frame – in many cases there is no need to perform calculations from scratch, updated results from previous frames can be used instead, if an update is required, (e) right choice when to perform the computation in an analog or in a digital way and (f) performing compute-intensive and power-hungry functions off-chip, if possible.
Power reduction through the circuit and logic level
1. Power reduction by leakage current control in analog and digital circuits[7]
Leakage is one of the main sources of power dissipation in "smart" image sensors. The following techniques can be employed to reduce the leakage .
(a) Differentiation between the "active" and "sleep" modes of the certain circuit by insertion of a "sleep" transistor (b) Reduction of the leakage current using the "stacked scheme" – by stacking two off transistors, the subthreshold current is reduced significantly compared to a single off device due to simultaneous reductions in gate-source, body bias, and drainsource voltages, © Multiple VTH design - applying different leakage control techniques, that usually are not used in image sensors design, like Multithreshold-voltage CMOS (MTCMOS), Variable Threshold CMOS (VTCMOS),, Dynamic VTH design, Cutoff CMOS (SC-CMOS) and others.
2. Low voltage operation [6]- reduction of the power supply voltage is a key element in low-power CMOS imagers. However, the design of a low voltage CMOS sensor involves several well-known challenges. Employing multiple voltage supplies can relax the problem. The idea of multiple VDD grows up from the dual-VDD approach of digital circuits design, where the gates of the non critical paths have the reduced supply voltage VDDL, while those on the critical paths have VDDH. This results in reducing the power without degrading the entire circuit
CMOS Image Sensor With dual VDD[5]
To improve the performance of CMOS image sensor ultra low power CMOS image sensor is used.Using dual VDD the power consumption of CMOS image sensor can be reduced. A low-power image sensor with dual analog power supply 1.8 and 1.1 V during image capture stage is used for ultra low power operation. Different from a traditional imager having a unique analog power for image capture, the CMOS imager with dual VDD works on blocks of 8 x 8 pixels and the power. The power supply is selected depending upon the voltage variation in the image For the blocks with large variance, high supply voltage will be chosen to achieve high imaging performance; otherwise, low supply voltage will be used to save power.
DYNAMIC RANGE ENHANCEMENT IN CMOS IMAGE SENSOR[13]
Power reduction is commonly achieved through technology scaling and aggressive supply voltage reduction these methods affects the dynamic range.Dynamic range quantifies the sensor's ability to adequately image both high lights and dark shadows in a scene ect the output swing of the sensor and thus decrease its dynamic range (DR).
Cpd represents the photodiode capacitance, upon which the charge is integrated Vmax and tmin represent the pixel swing and the minimal available integration time.imax and imin represent the maximum and minimum currents that can be detected by the sensor.
The narrow DR of image sensors causes the saturation of a pixel with high sensitivity, in the case of high illumination levels, resulting in a partial loss of information.The sensor dynamic range is 47dB . This dynamic range is not high enough to capture a typical outdoor scene where both bright sunlight and dark shadow exist. Several techniques and architectures have been proposed for extending image sensor dynamic range
ABSTRACT OF WORK
Different Imaging Systems are suitable for different purposes, de pending upon their final application.As the purposes are different, the technologies used differ from each other.Charge-coupled devices (CCDs) have traditionally been the dominant image-sensor technology.Recent advances in the design of imagesensors implemented in complementary metaloxidesemiconductor (CMOS) technologies have led to their adoption in several high products..For improving the performance of CMOS image sensor Power reduction techniques are necessary. Using dual power supply 37% of power can be saved for scene with predominant background
[attachment=66720]
INTRODUCTION
An image sensor is a device that converts an optical image into an electronic signal. It is used mostly in digital cameras, camera modules and other imaging devices.Most currently used image sensors are charge-coupled device (CCD) and complementary metal oxide–semiconductor (CMOS) sensors. Charge-coupled devices (CCDs) have traditionally been the dominant image-sensor technology. Recent advances in the design of image sensors implemented in complementary metaloxide semiconductor (CMOS) technologies have led to their adoption in several high-volume products, such as the optical mouse, PC cameras, mobile phones, and high-end digital cameras, making them a viable alternative to CCDs. For improving the performance of CMOS image sensor Power reduction techniques are necessary
Power Reduction Methods in Cmos Image Sensor
CMOS imagers naturally provide low-power dissipation, their wide utilization in various portable battery-operated devices generates an increased demand for more aggressive power reduction. There are many ways to reduce power dissipation in CMOS image sensors. Usually, the target is achieved by continuous technology
scaling and aggressive supply voltage reduction . However, in contrast to conventional digital circuits that achieve reduced area and better performance in state-of-the-art submicron processes, CMOS image sensors are more sensitive to technology scaling, requiring a stable, well-characterized technology. In addition to reduced photo collection efficiency and increased dark current, technology scaling and supply voltage reduction significantly affect the output swing of the sensor, producing a serious impact on the signal-to-noise ratio and dynamic range of the imager
Power Reduction at the Algorithm and Architecture Levels[2][3]
Power reduction through the algorithm selection is based on minimizing the number of operations and hence the number of required hardware resources. In conventional cameras-on-a-chip there are not so many options to reduce power dissipation through the algorithm level. Usually these imagers are limited by rolling or global shutter operation requirements and are expected to provide full resolution analog/digital grayscale/color image at the required frame rate . Many low power imagers are not required to provide a full resolution image at real time.
Power dissipation reduction at the algorithm level can be done by following methods (a) operational activity of different processing blocks should be reduced, (b) only windows of interest, consisting of the required features, should be defined and activated, while cutting off the remaining pixels of the array and periphery circuitry, responsible for their operation, © image transfer for further processing should be performed only in the cases where it is essential (d) computation of the required functions based on the computation results from the previous frame – in many cases there is no need to perform calculations from scratch, updated results from previous frames can be used instead, if an update is required, (e) right choice when to perform the computation in an analog or in a digital way and (f) performing compute-intensive and power-hungry functions off-chip, if possible.
Power reduction through the circuit and logic level
1. Power reduction by leakage current control in analog and digital circuits[7]
Leakage is one of the main sources of power dissipation in "smart" image sensors. The following techniques can be employed to reduce the leakage .
(a) Differentiation between the "active" and "sleep" modes of the certain circuit by insertion of a "sleep" transistor (b) Reduction of the leakage current using the "stacked scheme" – by stacking two off transistors, the subthreshold current is reduced significantly compared to a single off device due to simultaneous reductions in gate-source, body bias, and drainsource voltages, © Multiple VTH design - applying different leakage control techniques, that usually are not used in image sensors design, like Multithreshold-voltage CMOS (MTCMOS), Variable Threshold CMOS (VTCMOS),, Dynamic VTH design, Cutoff CMOS (SC-CMOS) and others.
2. Low voltage operation [6]- reduction of the power supply voltage is a key element in low-power CMOS imagers. However, the design of a low voltage CMOS sensor involves several well-known challenges. Employing multiple voltage supplies can relax the problem. The idea of multiple VDD grows up from the dual-VDD approach of digital circuits design, where the gates of the non critical paths have the reduced supply voltage VDDL, while those on the critical paths have VDDH. This results in reducing the power without degrading the entire circuit
CMOS Image Sensor With dual VDD[5]
To improve the performance of CMOS image sensor ultra low power CMOS image sensor is used.Using dual VDD the power consumption of CMOS image sensor can be reduced. A low-power image sensor with dual analog power supply 1.8 and 1.1 V during image capture stage is used for ultra low power operation. Different from a traditional imager having a unique analog power for image capture, the CMOS imager with dual VDD works on blocks of 8 x 8 pixels and the power. The power supply is selected depending upon the voltage variation in the image For the blocks with large variance, high supply voltage will be chosen to achieve high imaging performance; otherwise, low supply voltage will be used to save power.
DYNAMIC RANGE ENHANCEMENT IN CMOS IMAGE SENSOR[13]
Power reduction is commonly achieved through technology scaling and aggressive supply voltage reduction these methods affects the dynamic range.Dynamic range quantifies the sensor's ability to adequately image both high lights and dark shadows in a scene ect the output swing of the sensor and thus decrease its dynamic range (DR).
Cpd represents the photodiode capacitance, upon which the charge is integrated Vmax and tmin represent the pixel swing and the minimal available integration time.imax and imin represent the maximum and minimum currents that can be detected by the sensor.
The narrow DR of image sensors causes the saturation of a pixel with high sensitivity, in the case of high illumination levels, resulting in a partial loss of information.The sensor dynamic range is 47dB . This dynamic range is not high enough to capture a typical outdoor scene where both bright sunlight and dark shadow exist. Several techniques and architectures have been proposed for extending image sensor dynamic range
ABSTRACT OF WORK
Different Imaging Systems are suitable for different purposes, de pending upon their final application.As the purposes are different, the technologies used differ from each other.Charge-coupled devices (CCDs) have traditionally been the dominant image-sensor technology.Recent advances in the design of imagesensors implemented in complementary metaloxidesemiconductor (CMOS) technologies have led to their adoption in several high products..For improving the performance of CMOS image sensor Power reduction techniques are necessary. Using dual power supply 37% of power can be saved for scene with predominant background