29-08-2014, 10:28 AM
The main aim of this work is to design an AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-Performance Bus) protocol and verifying its functional behavior with the help of its simulation results.
Basic idea is to perform the proper and lossless communication between the IP cores which using same protocols on the System on Chip (SOC) system. Basically, an SOC is a system which is considered as a set of components and interconnects among them. The dataflow will happen in the system in order to achieve a successful process and hence for which the various interfaces are required. If these interfaces have issues, then the process to be achieved will fail which leads to fail of whole application.
Generally, in an SOC system, the protocols can be used as interfaces which will be based on the application and also the designer. The interface has its own properties which suits for the corresponding application. This project is chosen because currently the issues are increased in the industries due to the lack of proper data transferring between the IP cores on the System on Chip (SOC) system. In recent days, the development of SOC chips and the reusable IP cores are given higher priority because of its less cost and reduction in the period of Time-to-Market. So this enables the major and very sensitive issue such as interfacing of these IP cores. These interfaces play a vital role in SOC and should be taken care because of the communication between the IP cores property. The communication between the different IP cores should have a lossless data flow and should be flexible to the designer too. Hence to resolve this issue, the standard protocol buses are used in or order to interface the two IP cores. Here the loss of data depends on the standards of protocols used. Most of the IP cores from ARM uses the AMBA (Advanced Microcontroller Bus Architecture) which has AHB (Advanced High-Performance Bus). This bus has its own advantages and flexibilities. A full AHB interface is used for the following. 1. Bus masters. 2. On-chip memory blocks. 3. External memory interfaces. 4. High-bandwidth peripherals with FIFO interfaces. 5. DMA slave peripherals.
Basic idea is to perform the proper and lossless communication between the IP cores which using same protocols on the System on Chip (SOC) system. Basically, an SOC is a system which is considered as a set of components and interconnects among them. The dataflow will happen in the system in order to achieve a successful process and hence for which the various interfaces are required. If these interfaces have issues, then the process to be achieved will fail which leads to fail of whole application.
Generally, in an SOC system, the protocols can be used as interfaces which will be based on the application and also the designer. The interface has its own properties which suits for the corresponding application. This project is chosen because currently the issues are increased in the industries due to the lack of proper data transferring between the IP cores on the System on Chip (SOC) system. In recent days, the development of SOC chips and the reusable IP cores are given higher priority because of its less cost and reduction in the period of Time-to-Market. So this enables the major and very sensitive issue such as interfacing of these IP cores. These interfaces play a vital role in SOC and should be taken care because of the communication between the IP cores property. The communication between the different IP cores should have a lossless data flow and should be flexible to the designer too. Hence to resolve this issue, the standard protocol buses are used in or order to interface the two IP cores. Here the loss of data depends on the standards of protocols used. Most of the IP cores from ARM uses the AMBA (Advanced Microcontroller Bus Architecture) which has AHB (Advanced High-Performance Bus). This bus has its own advantages and flexibilities. A full AHB interface is used for the following. 1. Bus masters. 2. On-chip memory blocks. 3. External memory interfaces. 4. High-bandwidth peripherals with FIFO interfaces. 5. DMA slave peripherals.