04-09-2014, 04:32 PM
Implementation of High-Performance Image Scaling Processor using VLSI
[attachment=67645]
ABSTRACT
Inthis paper, a less complexity, less memory requirement, and high performance algorithm proposed for Very Large Scale Integration implementation of an image scaling processor. The anticipatedimage scaling algorithm consists of a clamp filter, spatial filter and a bilinear interpolation. The spatial and clamp filters are addedas pre-filters for reducing the aliasing artifacts resulted by the bilinear interpolation. A T-model and inversed T-model convolution kernels are proposed to reduce the complexity of the design. Combined filter is replaced by a dynamic estimation unit to minimize the hardware cost. This architecture is targeted to produce 320MHz with 6.08-K gate counts. Compared withPrevious methodologies, this workshows better performance with respect to cost and less complexity.
INTRODUCTION
IMAGE scaling has been widely applied in the fields of digital imaging and mainly on Electronic based imaging devices. Image scaling is the process of scaling down the high – quality frames or pictures to fit small size LCD panel of electronic displays as digital PDA’s are growing fast. Scaling algorithm can be classified into two types as polynomial-based and non-polynomial-based. Nearest neighbor algorithm is the uncomplicated polynomial algorithm, but resultant images are with full of aliasing artifacts. Bilinear interpolation algorithm and Bi-cubic algorithm are the other polynomial based method widely used to target the pixels.Adding of sharpening spatial and clamp filers effectively improves the image quality with bilinear interpolation algorithm. By these cost of the hardware and memory also reduced
[attachment=67645]
ABSTRACT
Inthis paper, a less complexity, less memory requirement, and high performance algorithm proposed for Very Large Scale Integration implementation of an image scaling processor. The anticipatedimage scaling algorithm consists of a clamp filter, spatial filter and a bilinear interpolation. The spatial and clamp filters are addedas pre-filters for reducing the aliasing artifacts resulted by the bilinear interpolation. A T-model and inversed T-model convolution kernels are proposed to reduce the complexity of the design. Combined filter is replaced by a dynamic estimation unit to minimize the hardware cost. This architecture is targeted to produce 320MHz with 6.08-K gate counts. Compared withPrevious methodologies, this workshows better performance with respect to cost and less complexity.
INTRODUCTION
IMAGE scaling has been widely applied in the fields of digital imaging and mainly on Electronic based imaging devices. Image scaling is the process of scaling down the high – quality frames or pictures to fit small size LCD panel of electronic displays as digital PDA’s are growing fast. Scaling algorithm can be classified into two types as polynomial-based and non-polynomial-based. Nearest neighbor algorithm is the uncomplicated polynomial algorithm, but resultant images are with full of aliasing artifacts. Bilinear interpolation algorithm and Bi-cubic algorithm are the other polynomial based method widely used to target the pixels.Adding of sharpening spatial and clamp filers effectively improves the image quality with bilinear interpolation algorithm. By these cost of the hardware and memory also reduced