10-09-2014, 11:40 AM
Stop Watch
[attachment=67773]
Abstract
This is the technical report for our ELEC 307 Project 2—Stop Watch. This project
is software and hardware co-design. We modeled the system in VHDL (Very-high-speed
integrated circuit Hardware Description Language) and implemented the system using a
FPGA board.
Introduction
Stop watch is timepiece equipment which is designed to measure the amount of
time elapsed from a particular time when activated to when it is deactivated. Our stop
watch has the most commonly used functionalities—Start, Pause and Reset.
We used Cyclone II FPGA board to implement our stop watch. The FPGA can be
programmed by our VHDL design. The board has internal clocks, on board push buttons
and on board LEDs. Therefore, we are going to make our design first in VHDL and
program the FPGA. We will use the internal clock to drive the entire system. Those on
board LEDs will be used to display each digit. We will use push buttons for the user
interaction. User can press buttons to either start, pause or reset the system.
Mod 6 & Mod 10 Counter:
Essentially, each digit of our stop watch is implemented as a modulo counter
(Figure 3). To be more specific, digits tenth second, second and minute are mod 10
counters because their values can only go from 0 to 9. Ten second, ten minute are mod
6 counters since their values can only go from 0 to 5. This also indicates that the
maximum range of our stop watch is from 00:00:0 to 59:59:9.
Seven-Segment Decoder
Each modulo counter will provide its corresponding digit in binary format. In
order to display them on the LEDs, we need a 4-to-7 decoder, which will decode each 4-
bit digit into 7-bit display format (Figure 4).
Procedure and Implementations
In order to accomplish this project, we first discussed how we should implement
this stop watch. We have two approaches: one is in algorithmic level and the other one
is in structural level. We decided to use the structural level model.
Then we started to test the hardware, such as the push buttons and LEDs. By
doing this, we figured out that both of them are low active. Therefore, we have to invert
all the values coming from the push buttons and going into the LEDs. We also figured
out the pin assignment of the clock, push buttons and LEDs. We also did plenty of testing on each individual component to make sure they
are correct both logically and functionally. After all the testing, we put all the
components together and did more testing to the system using waveforms. Then, we
downloaded our design to the board and tested on the hardware.
Results and Discussion
Initially, our design was in algorithmic level. We were trying to implement an up
counter. It takes the 10Hz clock from the clock converter and straight counts up until the
limit. Then the count value will go through a formatter. This formatter will format the
count value into time format, i.e. 00:00:0 formats. After that, we use seven-segment
decoders to decode each digit for display.
The Start, Pause and Reset functionality can be implemented and a finite state
machine (Figure 7) since we want to change its state only when we press the buttons
Standards and Society Impact
Stop watch has plenty of applications. It can be used to measure the time in
sports. Measure the presentation time or even measure the time during an exam. Since
our stop watch is implemented on FPGA, we can add other extensions to it. We can set
up a time and trigger some events when the stop watch reaches that time point.
Conclusion
In this project, we obtained more experience with Altera DE II board and how to
program a FPGA. Moreover, we learn more fundamental principles of designing digital
systems. In summary, this project is a good software hardware co-design practice.
[attachment=67773]
Abstract
This is the technical report for our ELEC 307 Project 2—Stop Watch. This project
is software and hardware co-design. We modeled the system in VHDL (Very-high-speed
integrated circuit Hardware Description Language) and implemented the system using a
FPGA board.
Introduction
Stop watch is timepiece equipment which is designed to measure the amount of
time elapsed from a particular time when activated to when it is deactivated. Our stop
watch has the most commonly used functionalities—Start, Pause and Reset.
We used Cyclone II FPGA board to implement our stop watch. The FPGA can be
programmed by our VHDL design. The board has internal clocks, on board push buttons
and on board LEDs. Therefore, we are going to make our design first in VHDL and
program the FPGA. We will use the internal clock to drive the entire system. Those on
board LEDs will be used to display each digit. We will use push buttons for the user
interaction. User can press buttons to either start, pause or reset the system.
Mod 6 & Mod 10 Counter:
Essentially, each digit of our stop watch is implemented as a modulo counter
(Figure 3). To be more specific, digits tenth second, second and minute are mod 10
counters because their values can only go from 0 to 9. Ten second, ten minute are mod
6 counters since their values can only go from 0 to 5. This also indicates that the
maximum range of our stop watch is from 00:00:0 to 59:59:9.
Seven-Segment Decoder
Each modulo counter will provide its corresponding digit in binary format. In
order to display them on the LEDs, we need a 4-to-7 decoder, which will decode each 4-
bit digit into 7-bit display format (Figure 4).
Procedure and Implementations
In order to accomplish this project, we first discussed how we should implement
this stop watch. We have two approaches: one is in algorithmic level and the other one
is in structural level. We decided to use the structural level model.
Then we started to test the hardware, such as the push buttons and LEDs. By
doing this, we figured out that both of them are low active. Therefore, we have to invert
all the values coming from the push buttons and going into the LEDs. We also figured
out the pin assignment of the clock, push buttons and LEDs. We also did plenty of testing on each individual component to make sure they
are correct both logically and functionally. After all the testing, we put all the
components together and did more testing to the system using waveforms. Then, we
downloaded our design to the board and tested on the hardware.
Results and Discussion
Initially, our design was in algorithmic level. We were trying to implement an up
counter. It takes the 10Hz clock from the clock converter and straight counts up until the
limit. Then the count value will go through a formatter. This formatter will format the
count value into time format, i.e. 00:00:0 formats. After that, we use seven-segment
decoders to decode each digit for display.
The Start, Pause and Reset functionality can be implemented and a finite state
machine (Figure 7) since we want to change its state only when we press the buttons
Standards and Society Impact
Stop watch has plenty of applications. It can be used to measure the time in
sports. Measure the presentation time or even measure the time during an exam. Since
our stop watch is implemented on FPGA, we can add other extensions to it. We can set
up a time and trigger some events when the stop watch reaches that time point.
Conclusion
In this project, we obtained more experience with Altera DE II board and how to
program a FPGA. Moreover, we learn more fundamental principles of designing digital
systems. In summary, this project is a good software hardware co-design practice.