25-08-2016, 10:01 AM
FPGA Implementation of BIST (Built in Self Test) Enabled UART For real time Interface applications
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ABSTRACT
Universal Asynchronous Receiver Transmitter is a kind of serial communication protocol. Mostly used for short –distance, low speed, low cost data exchange between computer and peripherals. BIST (BUILT IN SELF TEST) is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self testing, i.e., testing of their own operation using their circuits, there by reducing dependence external Automated Test Equipment (ATE).
Manufacturing process are extremely complex, inducting manufactures to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most popular test techniques is called Built in Self Test. A Universal Asynchronous Receiver /Transmit (UART) with BIST capability has the objectives of testing the UART on chip itself and no external devices are required to perform the test. Here VHDL Implementation of UART with embedded BIST capability using FPGA technology. The architecture of UART with BIST which tests the UART for its correctability.
In this project, the protocol of BIST Enabled UART is studied. The BIST Enabled UART architecture will be designed. Various blocks of BIST Enabled UART are modeled in VHDL. The design is functionally verified by simulating the code in ModelSim from Mentor Graphics. The FPGA synthesis is done using Xilinx ISE tool. The synthesis results of ISE are analyzed for timing and area. Various applications of designed BIST Enabled UART are studied.
[attachment=69821]
ABSTRACT
Universal Asynchronous Receiver Transmitter is a kind of serial communication protocol. Mostly used for short –distance, low speed, low cost data exchange between computer and peripherals. BIST (BUILT IN SELF TEST) is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self testing, i.e., testing of their own operation using their circuits, there by reducing dependence external Automated Test Equipment (ATE).
Manufacturing process are extremely complex, inducting manufactures to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most popular test techniques is called Built in Self Test. A Universal Asynchronous Receiver /Transmit (UART) with BIST capability has the objectives of testing the UART on chip itself and no external devices are required to perform the test. Here VHDL Implementation of UART with embedded BIST capability using FPGA technology. The architecture of UART with BIST which tests the UART for its correctability.
In this project, the protocol of BIST Enabled UART is studied. The BIST Enabled UART architecture will be designed. Various blocks of BIST Enabled UART are modeled in VHDL. The design is functionally verified by simulating the code in ModelSim from Mentor Graphics. The FPGA synthesis is done using Xilinx ISE tool. The synthesis results of ISE are analyzed for timing and area. Various applications of designed BIST Enabled UART are studied.