08-09-2016, 03:10 PM
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ABSTRACT
Universal Asynchronous Receiver Transmitter (UART) is widely used in data communication process especially for its advantages of high reliability, long distance and low cost. In this project, we present the design of 9-bit UART modules based on Verilog HDL. This design features automatic address identification in the character itself. We have implemented the VLSI design of the module and pass data between the proposed 9-bit UART module with a host CPU. The design consists of receiver module, transmitter module and prescaler module. We have explained the functions of each individual sub-modules and how the design works in simulation.
UART is a Universal Asynchronous Receiver Transmitter that performs parallel-to-serial conversion on data character received from the host processor into serial data stream, and serial-to-parallel conversion on serial data bits received from serial device to the host processor.
In a transmission, every Slave devices will search every character transmitted for address byte and try to match with its unique address. This results in a lot of wasted processing time for Slave devices. In a 9-bit network, UART uses the ninth bit of a character to differentiate between an address or a data character. By proposing the ninth bit for address byte indication, Slave devices are able to distinguish an address byte, compare the address and decide whether to accept or discard the following data bytes. This reduces the processing time of the Slave’s CPU.
ABSTRACT
Universal Asynchronous Receiver Transmitter (UART) is widely used in data communication process especially for its advantages of high reliability, long distance and low cost. In this project, we present the design of 9-bit UART modules based on Verilog HDL. This design features automatic address identification in the character itself. We have implemented the VLSI design of the module and pass data between the proposed 9-bit UART module with a host CPU. The design consists of receiver module, transmitter module and prescaler module. We have explained the functions of each individual sub-modules and how the design works in simulation.
UART is a Universal Asynchronous Receiver Transmitter that performs parallel-to-serial conversion on data character received from the host processor into serial data stream, and serial-to-parallel conversion on serial data bits received from serial device to the host processor.
In a transmission, every Slave devices will search every character transmitted for address byte and try to match with its unique address. This results in a lot of wasted processing time for Slave devices. In a 9-bit network, UART uses the ninth bit of a character to differentiate between an address or a data character. By proposing the ninth bit for address byte indication, Slave devices are able to distinguish an address byte, compare the address and decide whether to accept or discard the following data bytes. This reduces the processing time of the Slave’s CPU.