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ABSTRACT
Nanofluidics, the study and application of fluid flow in nanochannels/nanopores with at least
one characteristic size smaller than 100 nm, has enabled the occurrence of many interesting
transport phenomena and has shown great potential in both bio- and energy-related fields.
Nanochannels remain at the focus of growing scientific and technological interest. The
nanometer scale of the structure allows the discovery of a new range of phenomena that has
not been possible in traditional microchannels, among which a direct field effect control over
the charges in nanochannels is very attractive for various applications, since it offers a unique
opportunity to integrate wet ionics with dry electronics seamlessly. In this paper a highly
sensitive ions flow controller, for lab-on-a-chip devices, operating through the nanochannels
and low external potentials is demonstrated. The device is a fluidic-field-effect transistor
(Fluid-FET) which has nanodimensional fluidic channel.
INTRODUCTION
The area of micro/nano-fluidic systems for biomolecule detection, chemical reactors, drug
delivery etc. has got significant attention of scientific community over the last few years.
Material selection and device architecture are the two major concern for micro/nano-fluidic
industries. Fluid-Field Effect Transistor is a highly sensitive ions flow controller, for labon-a-chip
devices, operating through the nanochannels and low external potential. It’s ion
concentration can be modulated upto 50percent while working in sub-micro molar range.
The device has a nanodimensional fluidic channel, connecting two fluid reservoirs and is
capped with high quality thermal SiO2 (i.e., low surface charges compared with plasma enhanced
chemical vapor deposition SiO2), which is used as gate oxide; analogous to a channel
between sourcedrain of a conventional FET. The conductance of nanochannel is modeled
as a function of gate voltage and gate electrode position (symmetrical and asymmetrical
with respect to nanochannels). The precise movement of the ions in one preferred direction
(diodic behavior) is achieved by asymmetrically positioned external gate electrode.
Several nano-fluidic devices based on nano-pores and nanochannels have been reported to
produce ionic current modulation, for example by changing concentration or by patterning,
positively and negatively charged regions in conical nanopores. But these devices face major
limitation of conductivity modulation once they are made. Field effect transistors (FETs) in
semiconductors work on the principle of controlling the flow of electron in a semiconductor
channel by external third electrode. In the field effect control of the surface charges, an
electric potential also known as gate potential, is applied to the gate electrode patterned
along the outer surface of the dielectric channel wall. In nano-fluidic FET, the charge of
inner surface of nanochannel is modulated by gate potential which in turn controls the
movement of ions in nanochannels.
NANOFLUIDICS
Nanofluidics is the study and application of fluid flow in channels/pores with at least one
characteristic dimension below 100 nm[4]. The term nanofluidics has only recently been
introduced with the rise of micro total analysis systems(µT AS),which aim to integrate all
steps of biochemical analysis on one microchip. The roots of nanofluidics are broad, and
processes on the nanometer scale have implicitly been studied for decades in chemistry,
physics, biology, materials science, and many areas of engineering. This dynamic new field
has drawn attention in technology, biology, and medicine due to advances in biomolecule
preparation and analysis systems,single-molecule interrogations, and other unique modes of
molecular manipulation.
Electrokinetic effects in nanochannels
Electrostatics in liquids and electrokinetic effects, which are the most important and fundamental
concepts for the description of transport in nanofluidics. Fluid flow in nanochannels
is conveniently achieved by electrokinetic techniques or capillary forces. Pressure-driven flow
can also be used in nanochannels, but high pressures are needed to obtain fluid flow because
the pressure has a power-law relation with the height of the channel. In microchannels, fluid
manipulation with hydrostatic pressure is often used, but the achievement of well-controlled
fluid flow is challenging .This field covers electro-osmosis, electrophoresis, dielectrophoresis,
and electrorotation; here we emphasize electro-osmosis.
2.1.1 Electro-osmosis
If a charged[5] surface is in contact with a liquid and an electric field is applied parallel to
the interface, movement of liquid adjacent to the wall occurs. If the surface is negatively
charged, the net excess of positive ions in the Electric Double Layer(EDL) will draw the
liquid along because of viscous interactions, which results in flow toward the cathode. If
the EDL can develop fully in the nanochannel, the electric potential reduces to zero in the
center. However, if the ionic strength is low, the EDLs will overlap in the nanochannel and
affect electro-osmosis, which is no longer plug flow but instead follows the electric potential.
Electro-osmosis is the principle behind ion flow in Fluid-FET.
FLUID-FET
Fluid-FETs are realized using standard silicon process techniques with polysilicon as sacrificial
material, allowing thermally grown silicon oxide as capping layer with low surface
charges. The devices are analyzed using 3-D optical imaging, scanning electron microscopy,
and electrical characterization in the presence of various ionic solutions[1]. Fabrication of
nanochannel is done using sacrificial layer releasing.
FABRICATION DETAILS
The material selection for fluidic channel plays a key role in micro/ nano-fluidics. To assist
the filling of the fluidic channel without any external pumping, we use SiO2 as a fluidic
channel wall material because it is hydrophilic in nature. Fluid-FET is designed with channel
width of 7.5µm, height 0.2µm, length as 150µm, diameter of the reservoir is 2mm and gate
electrode is asymmetrically patterned with respect to nanochannel. Different nanochannels
fabrication techniques have been reported. Here, the sacrificial layer method has been used
to realize the Fluid-FET. Poly-silicon is used as a sacrificial layer which enables thermal
oxidation and this thermally grown SiO2 thus realized caps the nanochannel and works as
gate dielectric which makes this device novel on technology point of view. A metal electrode
4
is then patterned on it. Detailed process flow is elaborated in Fig.. First lithography is for
fluidic channel definition followed by 0.2 µm silicon RIE etched using CF4 for 3min. Then
thermal oxidation is done at 1050◦C to achieve 100nm thick silicon oxide. After thermal
oxidation, poly-silicon is filled in the nanochannels and fluid reservoirs using Low Pressure
Chemical Vapour Deposition(LPCVD) and the extra poly-silicon removal from the field
area by chemical mechanical polishing (CMP). Thermal oxidation is then accomplished to
achieve 0.15µm thick SiO2 as capping and gate dielectric followed by Ti/Au (200A◦/2000A◦
)
metallization and sintering at 450◦C for 30 minutes. Gate electrode is then patterned and
sacrificial layer is removed using wet etching.
ABSTRACT
Nanofluidics, the study and application of fluid flow in nanochannels/nanopores with at least
one characteristic size smaller than 100 nm, has enabled the occurrence of many interesting
transport phenomena and has shown great potential in both bio- and energy-related fields.
Nanochannels remain at the focus of growing scientific and technological interest. The
nanometer scale of the structure allows the discovery of a new range of phenomena that has
not been possible in traditional microchannels, among which a direct field effect control over
the charges in nanochannels is very attractive for various applications, since it offers a unique
opportunity to integrate wet ionics with dry electronics seamlessly. In this paper a highly
sensitive ions flow controller, for lab-on-a-chip devices, operating through the nanochannels
and low external potentials is demonstrated. The device is a fluidic-field-effect transistor
(Fluid-FET) which has nanodimensional fluidic channel.
INTRODUCTION
The area of micro/nano-fluidic systems for biomolecule detection, chemical reactors, drug
delivery etc. has got significant attention of scientific community over the last few years.
Material selection and device architecture are the two major concern for micro/nano-fluidic
industries. Fluid-Field Effect Transistor is a highly sensitive ions flow controller, for labon-a-chip
devices, operating through the nanochannels and low external potential. It’s ion
concentration can be modulated upto 50percent while working in sub-micro molar range.
The device has a nanodimensional fluidic channel, connecting two fluid reservoirs and is
capped with high quality thermal SiO2 (i.e., low surface charges compared with plasma enhanced
chemical vapor deposition SiO2), which is used as gate oxide; analogous to a channel
between sourcedrain of a conventional FET. The conductance of nanochannel is modeled
as a function of gate voltage and gate electrode position (symmetrical and asymmetrical
with respect to nanochannels). The precise movement of the ions in one preferred direction
(diodic behavior) is achieved by asymmetrically positioned external gate electrode.
Several nano-fluidic devices based on nano-pores and nanochannels have been reported to
produce ionic current modulation, for example by changing concentration or by patterning,
positively and negatively charged regions in conical nanopores. But these devices face major
limitation of conductivity modulation once they are made. Field effect transistors (FETs) in
semiconductors work on the principle of controlling the flow of electron in a semiconductor
channel by external third electrode. In the field effect control of the surface charges, an
electric potential also known as gate potential, is applied to the gate electrode patterned
along the outer surface of the dielectric channel wall. In nano-fluidic FET, the charge of
inner surface of nanochannel is modulated by gate potential which in turn controls the
movement of ions in nanochannels.
NANOFLUIDICS
Nanofluidics is the study and application of fluid flow in channels/pores with at least one
characteristic dimension below 100 nm[4]. The term nanofluidics has only recently been
introduced with the rise of micro total analysis systems(µT AS),which aim to integrate all
steps of biochemical analysis on one microchip. The roots of nanofluidics are broad, and
processes on the nanometer scale have implicitly been studied for decades in chemistry,
physics, biology, materials science, and many areas of engineering. This dynamic new field
has drawn attention in technology, biology, and medicine due to advances in biomolecule
preparation and analysis systems,single-molecule interrogations, and other unique modes of
molecular manipulation.
Electrokinetic effects in nanochannels
Electrostatics in liquids and electrokinetic effects, which are the most important and fundamental
concepts for the description of transport in nanofluidics. Fluid flow in nanochannels
is conveniently achieved by electrokinetic techniques or capillary forces. Pressure-driven flow
can also be used in nanochannels, but high pressures are needed to obtain fluid flow because
the pressure has a power-law relation with the height of the channel. In microchannels, fluid
manipulation with hydrostatic pressure is often used, but the achievement of well-controlled
fluid flow is challenging .This field covers electro-osmosis, electrophoresis, dielectrophoresis,
and electrorotation; here we emphasize electro-osmosis.
2.1.1 Electro-osmosis
If a charged[5] surface is in contact with a liquid and an electric field is applied parallel to
the interface, movement of liquid adjacent to the wall occurs. If the surface is negatively
charged, the net excess of positive ions in the Electric Double Layer(EDL) will draw the
liquid along because of viscous interactions, which results in flow toward the cathode. If
the EDL can develop fully in the nanochannel, the electric potential reduces to zero in the
center. However, if the ionic strength is low, the EDLs will overlap in the nanochannel and
affect electro-osmosis, which is no longer plug flow but instead follows the electric potential.
Electro-osmosis is the principle behind ion flow in Fluid-FET.
FLUID-FET
Fluid-FETs are realized using standard silicon process techniques with polysilicon as sacrificial
material, allowing thermally grown silicon oxide as capping layer with low surface
charges. The devices are analyzed using 3-D optical imaging, scanning electron microscopy,
and electrical characterization in the presence of various ionic solutions[1]. Fabrication of
nanochannel is done using sacrificial layer releasing.
FABRICATION DETAILS
The material selection for fluidic channel plays a key role in micro/ nano-fluidics. To assist
the filling of the fluidic channel without any external pumping, we use SiO2 as a fluidic
channel wall material because it is hydrophilic in nature. Fluid-FET is designed with channel
width of 7.5µm, height 0.2µm, length as 150µm, diameter of the reservoir is 2mm and gate
electrode is asymmetrically patterned with respect to nanochannel. Different nanochannels
fabrication techniques have been reported. Here, the sacrificial layer method has been used
to realize the Fluid-FET. Poly-silicon is used as a sacrificial layer which enables thermal
oxidation and this thermally grown SiO2 thus realized caps the nanochannel and works as
gate dielectric which makes this device novel on technology point of view. A metal electrode
4
is then patterned on it. Detailed process flow is elaborated in Fig.. First lithography is for
fluidic channel definition followed by 0.2 µm silicon RIE etched using CF4 for 3min. Then
thermal oxidation is done at 1050◦C to achieve 100nm thick silicon oxide. After thermal
oxidation, poly-silicon is filled in the nanochannels and fluid reservoirs using Low Pressure
Chemical Vapour Deposition(LPCVD) and the extra poly-silicon removal from the field
area by chemical mechanical polishing (CMP). Thermal oxidation is then accomplished to
achieve 0.15µm thick SiO2 as capping and gate dielectric followed by Ti/Au (200A◦/2000A◦
)
metallization and sintering at 450◦C for 30 minutes. Gate electrode is then patterned and
sacrificial layer is removed using wet etching.