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Abstract: - This Paper presents the work on implementation of Baugh-Wooley multiplier based on soft-core
processor. MicroBlaze soft core is high performance embedded soft core processor developed by XILINX
Company. This soft core enjoys high configurability and allows designer to make proper choice based on his
own design requirements to build his own hardware platform.
Custom hardware of power optimized Baugh-Wooley signed multiplier is interface with MicroBlaze soft core
processor. The major objective for using hardware for realizing Baugh-Wooley multiplier is to utilize hardware
for realizing fast and efficient processing capacity.
INTRODUCTION
Multipliers play an important role in today‟s digital signal processing and various other
applications. With advances in technology, many researchers have tried and are trying to design multipliers
which offer either of the following design targets – high speed, low power consumption, regularity of
layout and hence less area or even combination of them in one multiplier thus making them suitable
for various high speed, low power and compact implementation.
The common multiplication method is “add and shift” algorithm. In parallel multipliers number of partial
products to be added is the main parameter that determines the performance of the multiplier. To achieve speed
improvements Baugh-Wooley algorithm can be used.
This multiplier subsystem is commonly implemented using an embedded processor [1] combined with specific
hardware.
Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware
of circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to
more readily incorporate FPGAs in their designs. While FPGAs with soft processor cores provide designers
with increased flexibility.
Reconfigurable logic devices, such as field programmable gate arrays (FPGAs), have been very
effective to implement dedicated multiplier architectures . Over the last few years, the huge increase in FPGA
features made possible the implementation of a whole system in a single device: processor, peripherals,
memories and so on. Nowadays, it is feasible to implement on an FPGA an entire multiplication algorithm based
on a soft-core processor (SCP), which also includes multiplier cores for hardware acceleration .
There are a several soft core processors that are commonly used in SOC applications like PowerPC [5],
NIOS3 [4], MicroBlaze [2], and free or open cores that may be used without the need to acquire a license, like
LEON3 [6]. The main advantage of these processors are that they are usually well tested and optimized for a
specific target hardware and provide a complete set of CAD tools to make the SOC design an easier process. For
example, MicroBlaze from Xilinx is well integrated with the development platform from the same foundry,
which leads to highly optimized designs at the cost of being bound to a particular technology (Xilinx Spartan
and Virtex FPGA families ) and a concrete set of tools (Xilinx ISE and EDK
Microblaze Soft-Core Processor
MicroBlaze soft core is highly simplified embedded processor soft core with relatively high
performance developed by XILINX Company.[7] This soft core enjoys high configurability and allows
designer to make proper choice based on his own design requirements to build his own hardware platform. The
processor architecture includes thirty-two 32-bit general-purpose registers and an orthogonal instruction set. It
features a three-stage instruction pipeline, with delayed branch capability for improved instruction throughput.
As it is a SCP, the functional units incorporated into the processor architecture can be customized in order to fit
as much as possible the target application. This soft core adopts RISC instruction set and Harvard architecture
and has the following performance characteristics:
1) 32-bit general-purpose registers and 2 special register
2)32-bit instruction word length, 3 operands and 2 kinds of addressing modes.
3) Separated 32-bit instruction and data bus.
4) Complying with IBM OPB specification;
5) Local Memory Bus (LMB) enables direct access to on-chip block memory (BRAM), it provides highspeed
instructions and data caching and features three-stage pipelined architecture;
6) Hardware debugging module (MDM) and eight input/output fast link interfaces (FSL) are available. Figure
1 shows MicroBlaze‟s internal structure.
1.2 Multiplier [8]
Multiplication is a heavily used arithmetic operation that figures Multiplication is a heavily used
arithmetic operation that figures prominently in signal processing and scientific applications. Multiplication is
hardware intensive, and the main criteria of interest are higher speed, lower cost and lower power. The main
concern in classic multiplication often realized by K cycles of shifting and adding, is to speed up the underlying
multi-operand addition of partial products. A variety of multiplication algorithms and hardware designs are
available.
1.3 Baugh-Wooley Multiplier [7]
2‟s Compliments is the most popular method in representing signed integers in Computer sciences. It is
also an operation of negation(Converting positive to negative numbers or vice –versa) in computers which
represent negative numbers using two‟s compliments. Its use is so wide today because it does not require the
addition and subtraction circuitry to examine the signs of the operands to determine whether to add or subtract.
Two‟s compliment and one‟s compliment representations are commonly used since arithmetic units are simpler
to design. Figure 2 shows 2‟s compliment and one‟s compliment representations.
Baugh-Wooley Two‟s comp liment Signed numbers : Baugh-Wooley Two‟s compliment Signed multipliers is
the best known algorithm for signed multiplication because it maximizes the regularity of the multiplier and
allow all the partial products to have positive sign bits.Baugh–Wooley technique was developed to design direct
multipliers for Two‟s compliment numbers.When multiplying two‟s compliment numbers directly, each of the
partial products to be added is a signed numbers. Thus each partial produ ct has to be sign extended to the width
of the final product in order to form a correct sum by the Carry Save Adder (CSA) tree. According to Baugh- Wooley approach, an efficient method of adding extra entries to the bit matrix suggested to avoid having deal
with the negatively weighted bits in the partial product matrix.
CONCLUSION
This paper has described the process of implementation of Baugh-Wooley multiplier based on
MicroBlaze soft core processor. Since software implementation results in slower speed, so to increase the
computational speed, custom hardware of multiplier block is designed and interface with MicroBlaze processor.
Also VHDL code of multiplier is power optimized, takes 163 mW of power.
This fast and power optimized Baugh –Wooly multiplier hardware block can be used in future for
implementation of 8-bit FFT, 16 bit FFT, 32 bit FFT etc.
Abstract: - This Paper presents the work on implementation of Baugh-Wooley multiplier based on soft-core
processor. MicroBlaze soft core is high performance embedded soft core processor developed by XILINX
Company. This soft core enjoys high configurability and allows designer to make proper choice based on his
own design requirements to build his own hardware platform.
Custom hardware of power optimized Baugh-Wooley signed multiplier is interface with MicroBlaze soft core
processor. The major objective for using hardware for realizing Baugh-Wooley multiplier is to utilize hardware
for realizing fast and efficient processing capacity.
INTRODUCTION
Multipliers play an important role in today‟s digital signal processing and various other
applications. With advances in technology, many researchers have tried and are trying to design multipliers
which offer either of the following design targets – high speed, low power consumption, regularity of
layout and hence less area or even combination of them in one multiplier thus making them suitable
for various high speed, low power and compact implementation.
The common multiplication method is “add and shift” algorithm. In parallel multipliers number of partial
products to be added is the main parameter that determines the performance of the multiplier. To achieve speed
improvements Baugh-Wooley algorithm can be used.
This multiplier subsystem is commonly implemented using an embedded processor [1] combined with specific
hardware.
Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware
of circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to
more readily incorporate FPGAs in their designs. While FPGAs with soft processor cores provide designers
with increased flexibility.
Reconfigurable logic devices, such as field programmable gate arrays (FPGAs), have been very
effective to implement dedicated multiplier architectures . Over the last few years, the huge increase in FPGA
features made possible the implementation of a whole system in a single device: processor, peripherals,
memories and so on. Nowadays, it is feasible to implement on an FPGA an entire multiplication algorithm based
on a soft-core processor (SCP), which also includes multiplier cores for hardware acceleration .
There are a several soft core processors that are commonly used in SOC applications like PowerPC [5],
NIOS3 [4], MicroBlaze [2], and free or open cores that may be used without the need to acquire a license, like
LEON3 [6]. The main advantage of these processors are that they are usually well tested and optimized for a
specific target hardware and provide a complete set of CAD tools to make the SOC design an easier process. For
example, MicroBlaze from Xilinx is well integrated with the development platform from the same foundry,
which leads to highly optimized designs at the cost of being bound to a particular technology (Xilinx Spartan
and Virtex FPGA families ) and a concrete set of tools (Xilinx ISE and EDK
Microblaze Soft-Core Processor
MicroBlaze soft core is highly simplified embedded processor soft core with relatively high
performance developed by XILINX Company.[7] This soft core enjoys high configurability and allows
designer to make proper choice based on his own design requirements to build his own hardware platform. The
processor architecture includes thirty-two 32-bit general-purpose registers and an orthogonal instruction set. It
features a three-stage instruction pipeline, with delayed branch capability for improved instruction throughput.
As it is a SCP, the functional units incorporated into the processor architecture can be customized in order to fit
as much as possible the target application. This soft core adopts RISC instruction set and Harvard architecture
and has the following performance characteristics:
1) 32-bit general-purpose registers and 2 special register
2)32-bit instruction word length, 3 operands and 2 kinds of addressing modes.
3) Separated 32-bit instruction and data bus.
4) Complying with IBM OPB specification;
5) Local Memory Bus (LMB) enables direct access to on-chip block memory (BRAM), it provides highspeed
instructions and data caching and features three-stage pipelined architecture;
6) Hardware debugging module (MDM) and eight input/output fast link interfaces (FSL) are available. Figure
1 shows MicroBlaze‟s internal structure.
1.2 Multiplier [8]
Multiplication is a heavily used arithmetic operation that figures Multiplication is a heavily used
arithmetic operation that figures prominently in signal processing and scientific applications. Multiplication is
hardware intensive, and the main criteria of interest are higher speed, lower cost and lower power. The main
concern in classic multiplication often realized by K cycles of shifting and adding, is to speed up the underlying
multi-operand addition of partial products. A variety of multiplication algorithms and hardware designs are
available.
1.3 Baugh-Wooley Multiplier [7]
2‟s Compliments is the most popular method in representing signed integers in Computer sciences. It is
also an operation of negation(Converting positive to negative numbers or vice –versa) in computers which
represent negative numbers using two‟s compliments. Its use is so wide today because it does not require the
addition and subtraction circuitry to examine the signs of the operands to determine whether to add or subtract.
Two‟s compliment and one‟s compliment representations are commonly used since arithmetic units are simpler
to design. Figure 2 shows 2‟s compliment and one‟s compliment representations.
Baugh-Wooley Two‟s comp liment Signed numbers : Baugh-Wooley Two‟s compliment Signed multipliers is
the best known algorithm for signed multiplication because it maximizes the regularity of the multiplier and
allow all the partial products to have positive sign bits.Baugh–Wooley technique was developed to design direct
multipliers for Two‟s compliment numbers.When multiplying two‟s compliment numbers directly, each of the
partial products to be added is a signed numbers. Thus each partial produ ct has to be sign extended to the width
of the final product in order to form a correct sum by the Carry Save Adder (CSA) tree. According to Baugh- Wooley approach, an efficient method of adding extra entries to the bit matrix suggested to avoid having deal
with the negatively weighted bits in the partial product matrix.
CONCLUSION
This paper has described the process of implementation of Baugh-Wooley multiplier based on
MicroBlaze soft core processor. Since software implementation results in slower speed, so to increase the
computational speed, custom hardware of multiplier block is designed and interface with MicroBlaze processor.
Also VHDL code of multiplier is power optimized, takes 163 mW of power.
This fast and power optimized Baugh –Wooly multiplier hardware block can be used in future for
implementation of 8-bit FFT, 16 bit FFT, 32 bit FFT etc.