15-10-2016, 10:54 AM
[attachment=73074]
Busses.
Memory devices.
I/O devices:
serial links
timers and counters
keyboards
displays
analog I/O
The CPU bus
Bus allows CPU, memory, devices to communicate.
Shared communication medium.
A bus is:
A set of wires.
A communications protocol.
Bus protocols
Bus protocol determines how devices communicate.
Devices on the bus go through sequences of states.
Protocols are specified by state machines, one state machine per actor in the protocol.
May contain asynchronous logic behavior.
Bus mastership
By default, CPU is bus master and initiates transfers.
DMA must become bus master to perform its work.
CPU can’t use bus while DMA operates.
Bus mastership protocol:
Bus request.
Bus grant.
Flash writing
Write is much slower than read.
1.6 ms write, 70 ns read.
Blocks are large (approx. 1 Mb).
Writing causes wear that eventually destroys the device.
Modern lifetime approx. 1 million writes.
Busses.
Memory devices.
I/O devices:
serial links
timers and counters
keyboards
displays
analog I/O
The CPU bus
Bus allows CPU, memory, devices to communicate.
Shared communication medium.
A bus is:
A set of wires.
A communications protocol.
Bus protocols
Bus protocol determines how devices communicate.
Devices on the bus go through sequences of states.
Protocols are specified by state machines, one state machine per actor in the protocol.
May contain asynchronous logic behavior.
Bus mastership
By default, CPU is bus master and initiates transfers.
DMA must become bus master to perform its work.
CPU can’t use bus while DMA operates.
Bus mastership protocol:
Bus request.
Bus grant.
Flash writing
Write is much slower than read.
1.6 ms write, 70 ns read.
Blocks are large (approx. 1 Mb).
Writing causes wear that eventually destroys the device.
Modern lifetime approx. 1 million writes.